Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1999-12-29
2003-08-19
Heckler, Thomas M. (Department: 2185)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
Reexamination Certificate
active
06609209
ABSTRACT:
The present invention relates to computer systems and more particularly to reducing the power consumed by a processor within the computer system.
BACKGROUND
Computer systems, from small handheld electronic devices to medium-sized mobile and desktop systems to large servers and workstations, are becoming increasingly pervasive in our society. Computer systems typically include one or more processors. A processor manipulates and controls the flow of data in a computer by executing instructions. To provide more powerful computer systems for consumers, processor designers strive to continually increase the operating speed of the processor. Unfortunately, as processor speed increases, the power consumed by the processor tends to increase as well. Historically, the power consumed by the processor, and hence its speed, has been limited by two factors. First, as power consumption increases, the processor tends to run hotter, leading to thermal dissipation problems. Second, the power consumed by a processor may tax the limits of the power supply used to keep the processor operational, reducing battery life in mobile systems and diminishing reliability while increasing cost in larger systems.
Processor and computer system designers have developed numerous methods to deal with these issues. For example, processor designers implement specialized circuit design techniques that shut down the processor (or place the processor into a low power “sleep” mode) when the processor is idle for an extended period of time. Unfortunately, this technique may cause the computer system to be inefficient due to the latency associated with placing a processor into sleep mode and pulling the processor back out of sleep mode. For example, this technique may be unsuitable for placing the processor into a low power mode for short periods of time. What is needed is a faster and more dynamic power control technique.
The present invention addresses this and other problems associated with the prior art.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, a processor includes a pipeline having first and second stages and a shift register having first and second latches. An interface circuit is used to provide a clock signal from a clock signal line to the first and second stages based, at least in part, on first and second bits to be stored in the first and second latches, respectively.
Other features and advantages of the present invention will be apparent from the accompanying figures and the detailed description that follows.
REFERENCES:
patent: 5918042 (1999-06-01), Furber
patent: 6122751 (2000-09-01), Janssens et al.
patent: 6247134 (2001-06-01), Sproch et al.
Makineni Sivakumar
Medapati Suri B.
Sharma Vinod
Tiwari Vivek
Blakely , Sokoloff, Taylor & Zafman LLP
Heckler Thomas M.
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