Method and apparatus for reducing the apparent read latency when

Details Method and apparatus for reducing the apparent read latency when Method and apparatus for reducing the apparent read latency when

1997-05-14

1999-01-19

An, Meng-Al T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395306, 395308, 711143, G06F 1314

Patent

active

058623582

ABSTRACT:
An apparatus is provided for reducing read latency for an I/O device residing on a first bus having a first, short read latency timeout period. The apparatus includes a I/O bridge on a second bus having a second, longer read latency timeout compared to that of first bus which modifies read transactions into two separate transactions. A first transaction is a write transaction to the same address requested by the read transaction. This transaction forces a write-back if the address hits in a CPU's write-back cache. Thereafter the read transaction is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the first bus having a short read latency timeout period from exceeding it's read latency timeout limit.

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