Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-11-09
2001-05-01
Lefkowitz, Sumati (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C711S143000
Reexamination Certificate
active
06226703
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to computer systems and more particularly to computer systems having write-back caches.
As it is known in the art, certain I/O busses such as Digital Equipment Corporation's Q-bus™ have a short read latency timeout. A read latency timeout is defined as the longest period of time required by the system for satisfying a read request from an I/O device. For the Q-bus this read latency timeout is eight microseconds. Once an I/O device residing on the Q-bus does a read request transaction the requesting device waits for eight microseconds and if the requesting device hasn't received the data within this time period the requesting device assumes that there was a fault and declares a fatal error.
In some applications it is desirable to connect I/O busses having a short read latency timeout to a computer system including a Central Processor Unit (CPU) and a cache memory and in particular a write-back cache memory. Typical cache memory is relatively small, high-speed memory compared to main memory and is physically located close to the processor. In systems using cache memory with a CPU, the cache memory is typically provided to hold data which is most likely to be used by the processor.
A CPU will retrieve data from main memory, perform some operation on the data and eventually write this data back to main memory. The performance of a system is effected by the number of times a CPU performs read and write type operations to main memory. In order to reduce the number of operations the CPU performs with main memory many CPUs incorporate various cache memory techniques.
One technique used is the incorporation of a write-back cache. A write-back cache improves the performance of a system by limiting the number of write transactions to main memory. If a CPU seeks to perform a write operation to main memory, and the location is located in this CPU's cache (a cache hit), then the cache location is written to and it now contains the latest version of the data for that memory location. This saves the CPU from performing a write operation to main memory and results in an increase in performance. If the CPU requests a write to a memory location that is not in the cache (a cache miss) then the write to main memory is performed, or optionally the location can be allocated into the cache and then the write can be done into the cache.
One drawback to write-back caches occurs when the CPU is required to perform a write-back operation. Should a read from either a second CPU or from an I/O device hit in the first CPU's cache then the first CPU will stall the read transaction requested by the second CPU or I/O device, write the current version of the data out from the first CPU's write-back cache to main memory where it can be accessed by the requesting CPU or I/O device, and then allow the original requested transaction to complete. In this manner the original read transaction takes a longer time to complete since it waits for the write-back operation to occur before it can access the desired data.
Proper system operation requires that the system be able to satisfy read requests from I/O devices in a period of time less than or equal to the worst case read latency timeout limit for the bus the I/O device resides on. Accordingly in some cases it is possible for a read latency timeout to occur while performing a write back operation caused by a different read operation. For example, if a read is requested from an I/O device residing on an I/O bus having a short read latency timeout, this read can stall due to a currently executing read transaction from a device on a different I/O bus. This currently executing read stalls because the location requested by the read hits in the CPU's write-back cache. In response, the CPU will perform a write-back operation. The stalled read from the device on the different I/O bus is allowed to finish, and the read requested by the I/O device residing on the I/O bus having a short read latency timeout is then able to start. However, the device requesting this read may have timed out before this read can complete, due to the long wait caused by the previous read which resulted in a write-back operation. Should this timeout take place a fatal error is declared, and system operation halts.
SUMMARY OF THE INVENTION
In accordance with the present invention a method of operating a computer system including at least two I/O busses, a first one of the I/O busses having a short timeout period, the second one of the I/O busses having a longer timeout period than the first bus, including the steps of receiving a read transaction from an I/O device coupled to the second bus and performing a write transaction to the memory address specified in the read transaction is presented. The method further includes the steps of waiting a period of time before starting the read transaction on the second bus while permitting a transaction on the first bus to occur and, after the period of time has expired, performing the read transaction on the second bus to the memory address. With such an arrangement the computer system can be operated such that the first I/O bus having the short latency timeout period does not exceed its latency timeout limit.
In accordance with a further aspect of this present invention an I/O bridge including a timer, cycle decode logic having inputs coupled to means for interfacing to a first I/O bus, control logic having inputs coupled to outputs of said cycle decode logic, outputs of said control logic coupled to means for interfacing to a second I/O bus, with the timer coupled to the control logic, data path logic having a first set of input/output connections coupled to the means for interfacing to a first I/O bus, the data path logic having a second set of input/output connections coupled to the means for interfacing to a second I/O bus, cycle decode logic includes means responsive to a read transaction provided from the means for interfacing to a first I/O bus, means for initiating a write transaction to the means for interfacing to the second I/O bus, the control logic further includes means responsive to the write transaction from the cycle decode logic for starting the timer and for sending the read transaction after the timer has expired, means for interfacing the I/O bridge to a first bus having a longer read latency timeout period, means for interfacing said I/O bridge to a second I/O bus. With such an arrangement the computer system can be operated such that the first I/O bus having the short latency timeout period does not exceed its latency timeout limit.
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Crowell Jonathan
Ervin Joseph
Compaq Computer Corporation
Hamilton Brook Smith & Reynolds P.C.
Lefkowitz Sumati
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