Method and apparatus for reducing synthesis runtime

Details Method and apparatus for reducing synthesis runtime Method and apparatus for reducing synthesis runtime

2004-05-21

2008-08-19

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07415693

ABSTRACT:
A method for designing a system includes caching a representation of a first subnet with a synthesis result of the first subnet. The synthesis result of the first subnet is utilized for a second subnet in response to determining that a representation of the second subnet is identical to the representation of the first subnet.

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