Method and apparatus for reducing strapping devices

Details Method and apparatus for reducing strapping devices Method and apparatus for reducing strapping devices

2005-01-18

2005-01-18

Elamin, A. (Department: 2116)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C713S002000, C713S100000

Reexamination Certificate

active

06845444

ABSTRACT:
A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state. Subsequently, the configuration value fetched from the non-volatile memory is asserted to the at least one configurable device to configure the configurable device, and then the processor reset signal is deasserted, and the at least one configurable device is thereby completely configured.

REFERENCES:
patent: 5381452 (1995-01-01), Kowalski
patent: 5410722 (1995-04-01), Cornaby
patent: 5909557 (1999-06-01), Betker et al.
patent: 6269443 (2001-07-01), Poisner et al.
patent: 6434632 (2002-08-01), Hall
patent: 6625727 (2003-09-01), Moyer et al.

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