Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1999-12-23
2001-09-18
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S083000, C326S095000, C365S203000
Reexamination Certificate
active
06292029
ABSTRACT:
BACKGROUND
1. Field
An embodiment of the present invention relates to the field of integrated circuits and, more particularly, to reducing soft errors in integrated circuits that include dynamic circuits.
2. Discussion of Related Art
Dynamic circuits, such as domino circuits, for example, are widely used in high-speed integrated circuit designs. This is because dynamic circuits typically provide area and speed advantages over corresponding static complementary metal oxide semiconductor (CMOS) circuits.
Dynamic circuits, however, are more vulnerable to soft errors as compared to their static counterparts. A soft error is a transient, single event upset that changes the state of a circuit node or other internal storage element. Soft errors may, for example, be caused by alpha particles or cosmic rays impinging on the integrated circuit device.
Alpha particles are charged particles that may originate from the decay of trace impurities in integrated circuit packaging materials, for example. Cosmic rays may include heavy ions and protons that, either directly or indirectly, may have an ionization effect within the integrated circuit device semiconductor material. In either case, the charged particles from these sources may change the charge at an integrated circuit node such that the node actually transitions to an opposite logical state.
The critical charge (Qcrit) at a node is an indication of the susceptibility of the node to such soft errors. Qcrit is the minimum charge beyond which operation of a circuit will be affected. Thus, if an ion strike causes charge collected at a node to exceed Qcrit, the node may erroneously transition from a logical one state to a logical zero state, for example.
As integrated circuit fabrication technologies continue to scale down into the submicron region, less charge is stored on integrated circuit nodes and thus, less energy is needed to change the state of a node. For this reason, integrated circuit devices are becoming increasingly susceptible to soft error failures.
One approach to addressing this issue has been to add error detection and/or correction circuitry to integrated circuit designs. This approach may be used in memory design, for example. Error detection and/or correction circuitry identifies circuit errors such that resulting issues may be mitigated while correction circuitry may compensate for the error. Such approaches, while preventing some circuit failures, can involve significant additional circuitry that takes up valuable semiconductor real estate. Additionally, such approaches may not be viable for dynamic circuits in speed critical paths, for example.
Other approaches may involve processing changes. For some dynamic random access memory (DRAM) cells, for example, gate oxide thicknesses are decreased to store additional charge. This approach, however, may lead to an increase in other types of failures due to increased defects in the thinner gate oxide.
Other processing changes such as use of trench-capacitor structures, and applying a coating of a radioactive-contaminant-free polymer on top of an integrated circuit have also been used in an effort to reduce soft errors. Such processing changes may be undesirable because they add one or more additional processing steps involving additional time and expense. Further such approaches may not reduce soft errors to the extent desired.
SUMMARY OF THE INVENTION
A method and apparatus for reducing soft errors in a dynamic circuit are described. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.
REFERENCES:
patent: 4849658 (1989-07-01), Iwamura et al.
patent: 5065048 (1991-11-01), Asai et al.
patent: 5103113 (1992-04-01), Inui et al.
patent: 5144163 (1992-09-01), Matsuzawa et al.
patent: 5557620 (1996-09-01), Miller, Jr. et al.
patent: 6111434 (2000-08-01), Ciraula et al.
patent: 6191618 (2001-02-01), Gayles et al.
Jiang Wenjie
Kumar Sudarshan
Chang Daniel D.
Faatz Cynthia T.
Intel Corporation
Tokar Michael
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