Method and apparatus for reducing soft errors

Details Method and apparatus for reducing soft errors Method and apparatus for reducing soft errors

2003-12-22

2009-08-04

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C327S198000, C327S217000, C365S206000

Reexamination Certificate

active

07570508

ABSTRACT:
A method and apparatus for reducing soft errors in which the method includes: assigning a plurality of nodes within a storage circuit to a predetermined state; evaluating a plurality of signals coupled to the storage circuit, where evaluating the plurality of signals enables a first node to change from its predetermined state; and actively maintaining a second node in its predetermined state, where actively maintaining the predetermined state reduces the storage circuit's susceptibility to soft errors.

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R. Ramanarayanan et al., “Analysis of Soft Error Rate in Flip-Flops and Scannable Latches,” Microsystems Design Laboratory, 4 pp.
K. Mohanram et al. “Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits,” University of Texas at Austin, 9 pp.
English Abstract for JP 61-162895 A.
English Abstract for JP 09-312098 A.
English Abstract for JP 2001-23376 A.

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