Electronic digital logic circuitry – Accelerating switching
Patent
1998-12-22
2000-11-28
Tokar, Michael
Electronic digital logic circuitry
Accelerating switching
326 93, 326 83, 327170, 327108, H03K 1901, H03K 512, H03K 19175
Patent
active
061540455
ABSTRACT:
Alternately skewed gates to reduce signal transmission delay. For one embodiment, an integrated circuit includes a chain of gates alternately skewed for fast rise and fast fall. Pulse encoding logic coupled to the chain of gates pulse encodes a signal to be provided to and transmitted by the chain of alternately skewed gates.
REFERENCES:
patent: 4890016 (1989-12-01), Tanaka et al.
patent: 5383155 (1995-01-01), Ta
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5519344 (1996-05-01), Proebsting
patent: 5619146 (1997-04-01), Fujii et al.
patent: 5856746 (1999-01-01), Petrick
patent: 5926050 (1999-07-01), Proebsting
Hedenstierna, et al., "CMOS Circuit Speed and Buffer Optimization", IEEE Transactions on Computer-Aided Design. vol. CAD-6, No. 2 Mar. 1987, pp. 270-281.
Jason Cong, "Modeling and Layout Optimization of VLSI Devices and Interconnects In Deep Submicron Design", Department Of Computer Science, University of California, Los Angeles, pp. 1-6. No Date.
John Lillis, et al., "Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model", University of California, San Diego, pp. 1-6. No Date.
Lukas P.P.P. van Ginneken, "Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay", International Business Machines Corporation, Thomas J. Watson Research Center, Yorktown Heights, New York, 1990 IEEE, pp. 865-868.
Thompson, et al.; "Dual Threshold Voltages and Substrates Bias: Keys to High Performances, Low Power, 0.1 .mu.m Logic Designs"; 1997 Symposium on VLSI Technology Digest of Technical Papers; Jan. 1997; pp. 69-70.
Kawaguchi, et al.; "A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current"; IEEE International Solid-State Conference; Paper FP 12.4; Jan. 1998; pp. 192-193.
Mutoh, et al.; "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS"; IEEE Journal of Solid State Circuits; vol. 30 No. 8 Aug. 1995; pp. 847-854.
Halter, et al.; "A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits"; IEEE Custom Integrated Circuit Conference; Aug. 1997; pp. 1-4.
Kuroda, et al.; "A 0.9-V, 150-MHz, 10-mW, 4 mm.sub.2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme"; IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996; pp. 1770-1779.
De Vivek K.
Lu Shih-Lien
Narendra Siva
Ye Yibin
Chang Daniel D.
Intel Corporation
Tokar Michael
LandOfFree
Method and apparatus for reducing signal transmission delay usin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for reducing signal transmission delay usin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing signal transmission delay usin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1729360