Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-06-15
2003-04-01
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06543041
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a digital circuit design, and more specifically to a digital circuit design that uses a placement process and a routing process.
BACKGROUND OF THE INVENTION
Using Hardware Description Language (HDL), a digital circuit can be first designed at an abstract level (i.e. Register Transfer Level—RTL) in terms of its functionality and data flow. The functionality of the design is validated through simulation. A logic synthesis process then converts the RTL description to a gate-level netlist, which is a description of the circuit design in terms of gates and their connections. Using the gate-level netlist, a placement process generates a placed netlist, in which each of these gates is placed in a location on a chip floor. Based on the placed netlist, a routing process generates a physical layout by routing conducting lines to connect these gates. The physical layout for the digital circuit design can be finally fabricated onto a silicon chip.
Frequently, particular gate placement and connection patterns (or configurations) can cause signal integrity and reliability problems. For example, when two long conducting lines are closely arranged in parallel with each other, the parallel configuration can result in signals carried on one line interfering with the signals carried on the other nearby lines, and vice versa. This is the so called “crosstalk” problem. Traditionally, signal integrity and reliability problems are analyzed in the post-routing stage because these problems can be accurately analyzed after routing is complete.
One traditional solution to the problems is to make corrections to the physical layout based on the post-routing analysis. Unfortunately, it is difficult to correct these problems by modifying the physical layout. Most corrections require more chip resources (extra routing or extra gates), and a correction to one problem may cause other problems.
Another traditional solution to the problems is to modify the routing process to generate a new physical layout. However, routing modification at the post-routing stage allows only limited changes and this technique may not be able to find a solution without requiring revision of the placement process. It may take several reiterations of: post-routing analysis, routing modification, and placement modification. Because the traditional solution involves re-routing (including global-re-routing and local-re-routing) and re-placement, it is time consuming and not cost effective.
There is, therefore, a need for a method and apparatus to form a physical layout for a circuit design,with improved time and cost efficiency.
There is another need for a method and apparatus to form a physical layout for a circuit design with improved signal integrity and reliability in the post-routing stage.
There is yet another need for a method and apparatus to form a physical layout for a circuit design, which eliminate or reduce signal integrity and reliability problems in the post-routing stage, thus eliminating or reducing the modifications in the re-placement process or re-routing process.
The present invention provides a method and apparatus to meet these needs.
SUMMARY OF THE INVENTION
To address the shortcomings of the prior art, the present invention provides a novel method to form a physical layout for a circuit design.
In a broad aspect, the present invention provides a method for forming a physical layout on a chip floor based on a netlist for a circuit design. The netlist includes a plurality of gates. The method comprises the steps of: (a) assigning each of the gates to a location on the chip floor; (b) estimating potential signal integrity and reliability problems based on the assigned gate locations on the chip floor; (c) modifying the netlist based: on the estimation of the signal integrity and reliability problems, if the estimation made in step (b) is not acceptable; and (d) re-assigning each of the gates in the modified netlist in a location on the chip floor.
The present invention also provides a corresponding apparatus for performing the steps in the method described above.
REFERENCES:
patent: 5410490 (1995-04-01), Yastrow
patent: 5666288 (1997-09-01), Jones et al.
patent: 5726903 (1998-03-01), Kerzman et al.
patent: 5751593 (1998-05-01), Pullela et al.
patent: 5880967 (1999-03-01), Jyu et al.
patent: 5883818 (1999-03-01), Salimi et al.
patent: 5917728 (1999-06-01), Ueda
patent: 5917729 (1999-06-01), Naganuma et al.
patent: 5974245 (1999-10-01), Li et al.
patent: 5987086 (1999-11-01), Raman et al.
patent: 5995732 (1999-11-01), Murai
patent: 6086628 (2000-07-01), Dave et al.
patent: 6230304 (2001-05-01), Groeneveld et al.
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6311147 (2001-10-01), Tuan et al.
patent: 6321364 (2001-11-01), Hirata
patent: 6353917 (2002-03-01), Muddu et al.
NN9410491 (“Technique for Current Detection in Power Converters”, IBM Technical Disclosure Bulletin, vol. 37, No. 10, Oct. 1994, pp. 491-494 (4 pages)).*
NN9407165 (“Electromagnetic Interference Reduction through Time Distribution of Clock Signals”, IBM Technical Disclosure Bulletin, vol. 37, No. 7, Jul. 1994, pp. 165-168 (5 pages)).*
NN9105353 (“Modeling Large CMOS Circuits”, IBM Technical Disclosure Bulletin, vol. 33, No. 12, May 1991, p. 353 (4 pages)).*
NN9009396 (“Technique for Sizing Input Capacitance in Off-Line Power Converters”, IBM Technical Disclosure Bulletin, vol. 33, No. 4, Sep. 1990, pp. 396-400 (7 pages)).*
Yang et al. (“Switch-level timing simulation of bipolar ECL circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 4, Apr. 1993, pp. 516-530).*
NN9210409 (“Algorithm to Calculate Data Used by Logic Synthesis of Timing Critical Designs”, IBM Technical Disclosure Bulletin, vol. 35, No. 5, Oct. 1992, pp. 409-411 (5 pages)).*
NB83123672 (“Circuit Structure for Measuring Delays of Logic Gates on VLSI Chips”, IBM Technical Disclosure Bulletin, vol. 26, No. 7B, Dec. 1983, pp. 3672-3674 (6 pages)).*
NN9201230 (“Method of Generating Net Resistance Constraints From RC Delay”, IBM Technical Disclosure Bulletin, vol. 34, No. 8, Jan. 1992, pp. 230-232 (5 pages)).*
NB9309301 (“Allocating Maximum RC Delays to Guarantee Timing by Depth First Search”, IBM Technical Disclosure Bulletin, vol. 36, No. 9B, Sep. 1993, pp. 301-304 (9 pages)).*
Venkataraman et al. (“Trade-offs between yield and reliability enhancement [VLSI]”, Proceedings of 1996 IEEE International Symposium on Defect and Fault Tolerence in VLSI Systems, Nov. 6, 1996, pp. 68-76).*
Balboni et al. (“Clock skew reduction in ASIC logic design: a methodology for clock tree management”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, No. 4, Apr. 1998, pp. 344-356).*
Tenbroek et al. (“Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques”, IEEE Transactions on Electron Devices, vol. 43, No. 12, Dec. 1996, pp. 2240-2248).*
Jagau (“SIMCURRENT-an efficient program for the estimation of the current flow of complex CMOS circuits”, 1990 IEEE International Conference on Computer-Aided Design, ICCAD-90, Digest of Technical Papers, Nov. 11, 1990, pp. 396-399).*
Roy et al. (“Logic synthesis for reliability: an early start to controlling electromigration and hot-carrier effects”, IEEE Transactions on Reliability, vol. 44, No. 2, Jun. 1995, pp. 251-255).
Salowe Jeffrey S.
Scheffer Louis K.
Cadence Design Systems Inc.
Carpenter John W.
Kik Phallaka
Reed Smith Crosby Heafey LLP
Smith Matthew
LandOfFree
Method and apparatus for reducing signal integrity and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for reducing signal integrity and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing signal integrity and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3009040