Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Patent
1997-09-30
1999-11-30
Tokar, Michael
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
326 31, H03K 1716, H03K 19003
Patent
active
059949198
ABSTRACT:
A clamping circuit is provided to reduce ringing of digital signals delivered over a transmission line. The clamping circuit includes a pair of transistors respectively connecting the transmission line to a pair of voltage supplies, such as a V.sub.supply and ground. The transistors are controllably enabled to connect the transmission line to V.sub.supply or ground in response to a transition in the digital signal present on the transmission line. That is, the transistor interconnecting the transmission line to ground is controllably enabled in response to a high-to-low transition so as to counteract ringing on the transmission line. Alternately, the transistor interconnecting the transmission line to V.sub.supply is controllably enabled in response to a low-to-high transition so as to counteract ringing on the transmission line.
REFERENCES:
patent: 5563539 (1996-10-01), Takase
patent: 5638328 (1997-06-01), Cho
patent: 5801550 (1998-09-01), Tanaka et al.
Intel Corporation
Jean Pierre Peguy
Tokar Michael
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