Method and apparatus for reducing radiation and cross-talk...

Electronic digital logic circuitry – Reliability – Redundant

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S156000

Reexamination Certificate

active

08054099

ABSTRACT:
The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.

REFERENCES:
patent: 5870332 (1999-02-01), Lahey et al.
patent: 6127864 (2000-10-01), Mavis et al.
patent: 6326809 (2001-12-01), Gambles et al.
patent: 6480019 (2002-11-01), Waldie et al.
patent: 6504411 (2003-01-01), Cartagena
patent: 6882201 (2005-04-01), Koch et al.
patent: 7269057 (2007-09-01), Haddad et al.
patent: 7482831 (2009-01-01), Chakraborty et al.
patent: 7590907 (2009-09-01), Drake et al.
patent: 2001/0038304 (2001-11-01), Waldie et al.
patent: 2005/0265089 (2005-12-01), Lotz et al.
patent: 2007/0028157 (2007-02-01), Drake et al.
patent: 2007/0132496 (2007-06-01), Kuboyama
patent: 2008/0115023 (2008-05-01), Carlson
patent: 2009/0189634 (2009-07-01), Rezgui et al.
Naseer et al., “The DF-DICE Storage Element for Immunity to Soft Errors”, Proceedings of the 48th IEEE International Midwest Symposium on Circuits and Systems, 2006, pp. 303-306.
Blum et al., “Comparison of SET-Resistant Approaches for Memory-Based Architectures”, Proceedings of the 12th NASA Symposium VLSI Design, 2005, pp. 1-6.
“PrimeTime—Golden Timing SignOff Solution and Environment”, Synopsys, pp. 1-5, retrieved Jun. 16, 2009 http://www.synopsys.com/Tools/Implementation/SignOff/Pages/PrimeTime.aspx.
“PrimeTime—Golden Timing SignOff Solution and Environment”, Synopsys Datasheet, pp. 1-6, retrieved Jun. 16, 2009 http://www.synopsys.com/Tools/Implementation/SignOff/Documents/primetime—suite—ds.pdf.
“CeltIC”, Cadence Datasheet, pp. 1-2 retrieved Jun. 16, 2009 http://w2.cadence.com/datasheets/3073E—CeltIC—DS—Fnl.pdf.
Li, Uyhong et al., “Low Power Dissipation SEU-hardened CMOS Latch”, PIERS Online, vol. 3, No. 7, 2007, pp. 1080-1084.
USPTO office action for U.S. Appl. No. 13/015331 dated Mar. 4, 2011.
EP Search report for application EP10251339 dated Dec. 20, 2010.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for reducing radiation and cross-talk... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for reducing radiation and cross-talk..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing radiation and cross-talk... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4276878

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.