Method and apparatus for reducing processor bus loading

Details Method and apparatus for reducing processor bus loading Method and apparatus for reducing processor bus loading

1999-12-10

2002-10-15

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S144000, C711S145000

Reexamination Certificate

active

06467031

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an input/output agent accessing memory, and more specifically, to the I/O agent accessing coherent cache lines.
BACKGROUND
Maintaining cache coherency between I/O agents and processor agents generally requires a single coherency point to communicate the state of cache lines between the entities that might want to access them. Traditionally, this coherency point has been the processor bus. Thus, all accesses to coherent cache lines have been required to traverse this coherency point in order to properly sequence accesses to coherent memory between agents.
FIG. 1
illustrates a flowchart of a prior art memory access by an I/O agent. The process starts at block
110
.
At block
120
, the I/O agent sends a request for 16 bytes of information to the memory controller. The I/O agent generally addresses the memory controller that forwards I/O agent requests appropriately.
At block
130
, the memory controller initiates a snoop of the processor bus to determine ownership of the data. Generally, for cache coherency reasons, the processor bus is snooped.
At block
140
, the process determines whether the processor cache owns the data. If the processor cache owns the data, the processor returns the 16 bytes of data to the I/O agent.
If the processor does not own the data, the memory controller obtains the data from the memory and returns the requested 16 bytes of data to the I/O agent.
This method is reasonable, as long as the access sizes used by the I/O agent are identical to the access granularity of the processor bus and memory. However, if the I/O devices attempt to access coherent memory at a finer granularity than that used by the processor bus, then the overhead on the processor bus balloons by the ratio of the bus access size to the I/O access size. For example, an I/O agent that attempts to access coherent memory 16 bytes at a time—as shown in FIG.
1
—where the processor bus uses 64 byte granularity loads the processor bus at four times the rate of an I/O agent that uses 64 byte memory access. For systems in which the I/O devices access memory at a finer granularity than the granularity of the processor bus, the process shown in
FIG. 1
is disadvantageous.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a method of reducing processor bus loading in a system having a processor with a first processor bus granularity, a memory controller, and an ownership tracker is provided. First, a set of data is requested from a memory controller, the set of data being smaller than the processor bus granularity. If the memory controller does not own the set of data, the memory controller performs a processor bus snoop to determine if a processor cache owns the set of data. If the processor cache owns the set of data, the memory controller is assigned ownership of a block of data having a size equal to the processor bus granularity. The memory controller returns the set of data requested by an I/O agent to the I/O agent.


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Sweazey, “VLSI Support for Copyback Caching Protocols on Futurebus,” IEEE, pp. 240-246, 1988.

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