Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-13
2004-03-23
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06711719
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and apparatus for reducing power consumption in VLSI circuit designs. More particularly, the invention relates to a method and apparatus for causing a load capacitance connected to a source circuit in an IC (integrated circuit) design to be blocked or “isolated” from the source, given appropriate conditions, thereby reducing overall power consumption.
VLSI circuit designs, for example, CMOS ASICs (Application Specific Integrated Circuits) typically include source or driving cells connected to one or more driven or sink cells. The term “cell” as used herein refers to components of IC designs. In pre-fabrication stages, an IC design may be expressed in some form of digital data as an organization of standardized logic elements. Such standardized logic elements are commonly referred to as “cells” and are available from a number of vendors. The cells are typically stored as digital data in a library (and consequently are also sometimes called “books”). Examples of relatively low-level library cells include the standard Boolean circuits.
Cells may exist at different hierarchical levels. A plurality of cells may be organized into a higher-order structure which may also be identified as a cell; an example is an adder. A plurality of such higher-order structures may themselves be organized into a still-higher-order structure, and so on up to the highest or chip-level cell.
An IC design may also be referred to as an electrical “network” of interconnected cells, and accordingly connections between cells for propagating signals from one cell to another are often referred to as “nets.” In the early design stages of the IC, when the IC is typically represented in software for ease of testing and debugging, a net is a logical connection. During later design stages, when physical placement of the cells on the IC is known (physical implementation phase), the net is digitally represented as a physical connection. When the IC is fabricated, a net becomes a physical connection via some conductive medium, and a cell becomes a physical circuit. Accordingly, a capacitive load is experienced by a source cell connected via a net or plurality of nets to driven or sink cells. Nets may also be referred to as “wires” or the “wiring” of the IC.
It may further be appreciated that whether a cell is referred to as a “source” or driving cell, or a “sink” or driven cell depends on the perspective within the network from which the cell is viewed. A cell may be a source cell with respect to “downstream” cells; i.e., cells that it drives or to which it propagates a logic signal; and a sink cell with respect to “upstream” cells; i.e., cells by which it is driven or which propagate logic signals to it.
Source and sink cells are constituents of “logic cones.” The term “logic cone” refers to a grouping of cells involved in performing some logical function of the IC design. A logic cone may be determined with respect to an individual cell by identifying every downstream cell whose logic state it could influence; thus, the term “cone” is descriptive of a typically fan-like pattern that may be observed as downstream sink cells affected by a given source cell are traced out. The logic cone terminates at one or more observable points, i.e., for example, a clocked latch or a primary output of the function supported by the logic cone. A primary output could be, for example, an output pin of a chip housing the design.
In IC designs as described above, a component of power consumed may be represented as Power=½ FCV
2
, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. On large CMOS VLSI chips, for example, capacitance from wiring interconnect can be a significant portion of the capacitive load being driven by the source cell.
However, not every signal value generated by a source cell on a net is required to propagate to all the sink cells connected to the net for every clock cycle of a chip. Sections of logic (multiple cones) can be turned off by having the clock or data associated with their latches forced to be inactive, this is commonly referred to as putting the logic in sleep mode. Due to the Boolean function of the cells contained within the logic cone signal propagation could be blocked before it reaches a storage element (“latch”) or other observable output of the chip if the downstream logic's Boolean function prevents the signal from propagating. The signal causes no observable result.
As another example of a case when a signal causes no observable result, consider a source cell which drives one input of a two-input OR gate, where it is known that the other of the inputs to the OR gate is high. In such a case, it does not matter what the input driven by the source cell is, since the output of the OR gate will be high regardless of this input.
In view of the above, a method and apparatus are needed for realizing a reduction in power consumed by the propagation of signals which cause no observable result.
SUMMARY OF THE INVENTION
In a method and apparatus according to the present invention, a reduction in power expenditure is achieved by isolating source cells from the load capacitance of a downstream sink cell or cells when a signal output by the source cell will cause no observable results, and therefore need not be propagated to the downstream sink cell or cells.
According to one embodiment, an “isolate” cell is introduced into an IC design for selected source cells. The isolate cell is placed in a net connecting a selected source cell and at least one sink cell, between the selected source cell and at least one sink cell. The isolate cell is controlled by an isolate function to isolate the source cell from a portion of the net and the at least one sink cell when a signal generated by the source cell will cause no observable downstream results. By isolating the source cell from the net portion and at least one sink cell, the load capacitance of the net portion and at least one sink cell is not experienced by the source cell, thereby reducing the “C” factor in the above expression for power consumed by a network.
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Cohn John Maxwell
Dean Alvar A.
Farrahi Amir H.
Hathaway David J.
Lepsic Thomas Michael
Connolly Bove & Lodge & Hutz LLP
International Business Machines - Corporation
Kik Phallaka
Smith Matthew
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