Method and apparatus for reducing power consumption in an...

Details Method and apparatus for reducing power consumption in an... Method and apparatus for reducing power consumption in an...

2007-08-14

2007-08-14

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

11182100

ABSTRACT:
A system that reduces power consumption in an integrated circuit. During operation the system receives a placement for the integrated circuit. The system then groups registers in the placement into clusters and builds a temporary clock tree for the registers within the placement. Next the system assigns net weights to clock wires in the temporary clock tree and signal wires between the rest of the cells of the circuit, and uses the assigned net weights to optimize placement of the cells of the circuit by minimizing a sum of the weighted costs of the wires, wherein the weighted cost of a wire is a product of the net weight of the wire and the length of the wire.

REFERENCES:
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 6216252 (2001-04-01), Dangelo et al.

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