Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1997-06-30
1999-12-21
Tokar, Michael
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326119, 326121, H03K 19096
Patent
active
060054174
ABSTRACT:
A method and apparatus for reducing power consumption in a domino logic is provided. An input of the domino logic block has as an output of an upstream logic block. A first state, e.g. default or idle, of the output of the upstream logic block is determined. The an output of the domino logic block corresponding to the said first state is determined. A logic block is modified, such that the output of the domino logic block for the first state is the same as a precharge state of the output. This results in preventing the output of the domino logic block from toggling when the first state is the input to the domino logic block.
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Cheng Tsai-Chu
Mehta Gaurav G.
Simone Chris L.
Sin Chi-Kai
Sotoudeh Yahya
Intel Corporation
Le Don Phu
Tokar Michael
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