Method and apparatus for reducing power consumption in a...

Details Method and apparatus for reducing power consumption in a... Method and apparatus for reducing power consumption in a...

2006-09-12

2006-09-12

Auve, Glenn A. (Department: 2111)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C710S100000, C710S104000

Reissue Patent

active

RE039284

ABSTRACT:
A power management mechanism for use in a computer system having a bus, a memory for storing data and instructions, and a central processing unit (CPU). The CPU runs an operating system having a power management virtual device driver (PMV×D) responsible for performing idle detection for devices. The PMV×D performs idle detection using event timers that provide an indicator as to the activity level. The PMV×D places idle local devices in a reduced power consumption state when no activity has occurred for a predetermined period of time.

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patent: 5404321 (1995-04-01), Mattox
patent: 5404546 (1995-04-01), Stewart
patent: 5560022 (1996-09-01), Dunstan et al.
Intel Corporation, “Power Management Coordinator API Specification,” Apr., 1994.

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