Electrical computers and digital processing systems: processing – Instruction decoding
Reexamination Certificate
2005-02-22
2005-02-22
Jean, Frantz B. (Department: 2151)
Electrical computers and digital processing systems: processing
Instruction decoding
C712S219000, C712S233000
Reexamination Certificate
active
06859871
ABSTRACT:
The invention provides techniques for reducing the power consumption of pipelined processors. In an illustrative embodiment, the invention evaluates the predicates of predicated instructions in a decode stage of a pipelined processor, and annuls instructions with false predicates before those instructions can be processed by subsequent stages, e.g, by execute and writeback stages. The predicate dependencies can be handled using, e.g., a virtual single-cycle execution technique which locks a predicate register while the register is in use by a given instruction, and then stalls subsequent instructions that depend on a value stored in the register until the register is unlocked. As another example, the predicate dependencies can be handled using a compiler-controlled dynamic dispatch (CCDD) technique, which identifies dependencies associated with a set of instructions during compilation of the instructions in a compiler. One or more instructions are then grouped in a code block which includes a field indicating the dependencies associated with those instructions, and the instructions are then, e.g., either stalled or decoded serially, based on the dependencies present in the code block. By eliminating unnecessary processing for false-predicate instructions, the invention significantly reduces the power consumption of the processor.
REFERENCES:
patent: 5471593 (1995-11-01), Branigin
patent: 5590351 (1996-12-01), Sowadsky et al.
patent: 5761476 (1998-06-01), Martell
patent: 5799180 (1998-08-01), Shiell et al.
patent: 5857104 (1999-01-01), Natarjan et al.
patent: 5933618 (1999-08-01), Tran et al.
patent: 5991874 (1999-11-01), Mill et al.
patent: 6157996 (2000-12-01), Christie et al.
D.A. Patterson and J.L. Hennessy, “Computer Architecture: A Quantitative Approach,” Second Edition, Morgan Kaufmann, San Francisco, CA, pp. 240-261, 300-303, 1996.
Texas Instruments TMS320C62xx Technical Brief, Lit. No. SPRU197, Jan. 1997.
Batten Dean
D'Arcy Paul Gerard
Glossner C. John
Jinturkar Sanjay
Thilo Jesse
Agere Systems Inc.
Jean Frantz B.
LandOfFree
Method and apparatus for reducing power consumption in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for reducing power consumption in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing power consumption in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3513190