Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-01-29
2008-01-29
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C430S005000, C430S030000
Reexamination Certificate
active
07325225
ABSTRACT:
It is important to assess and reduce errors that arise in mask correction techniques such as optical proximity correction. A preliminary mask is obtained using an OPC model. An etched wafer is created from the preliminary mask using lithography, and first and second critical dimensions (CD) are measured on the wafer and. An edge placement error (EPE) is determined that corresponds to a difference between a measured value and a desired value of the second CD. These steps are repeated for a plurality of different values of the first CD, and of for each of the values of, the measured value of the second CD is correlated with its corresponding value on the mask as predicted by the OPC model. Δ difference ΔCD is obtained between the difference of the mask CDs calculated by interpolation of wafer CD measurements and by OPC model predictions and is transformed into an OPC model error.
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Angyal Matthew
Inohara Masahiro
Tanaka Yasushi
Chiang Jack
Doan Nghia M.
Mayer & Williams PC
Williams Esq. Karin L.
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