Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2003-07-31
2004-09-21
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S742000, C438S754000
Reexamination Certificate
active
06794304
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication, and more particularly to a dual damascene process used in semiconductor fabrication.
BACKGROUND OF THE INVENTION
In the field of semiconductor fabrication, a pathway, hole, or other passage through a substrate of an integrated circuit is known as a “via”. The via can be filled with an electrically conductive material, such as a metal, so that electrical current can flow to or from a metal line, i.e., a metal contact, that is embedded in the substrate at an end of the via.
During the formation of an integrated circuit, transistor devices are fabricated on semiconductor material, such as silicon. A dielectric layer is deposited over the transistor devices. Conductive plugs extend from the bottom surface to the top surface of the dielectric layer, enabling electrical contact with the transistors to be achieved through the dielectric layer. A film having a low dielectric constant K is then deposited over the dielectric layer. Metal lines extend from the bottom surface to the top surface of the low K film, enabling electrical contact with the conductive plugs and the transistors to be achieved through the low K film. Thus, the metal lines can be used to electrically connect the outside world to the transistors within the integrated circuit.
The low K film with the metal lines embedded therein is further covered with an insulating layer of electrically nonconductive material. Thus, the metal line is disposed below the upper surface of the integrated circuit. By forming a via through the nonconductve material and filling the via with conductive material, it is possible to make an electrical connection to the metal line at different vertical levels, thereby allowing access to the metal line from outside of the integrated circuit. Such arrangements are used to provide external contacts for integrated circuits.
In the lithography process of semiconductor fabrication, an attempt is made to create the via in a location that is aligned with the underlying metal line so that electrical communication can be established between the metal line and an electrically conductive material that will fill the via. In order to make the alignment easier, it is known to provide the metal line with an area of increased width, known as a “landing pad”, through which the metal line makes electrical contact with the conductive material inside the via.
FIG. 1
illustrates a metal line
20
having such a landing pad
22
of increased width W. The landing pad
22
is aligned with a via
24
.
In order to minimize circuit size and maximize transistor density, the widths of metal lines and vias have been reduced in succeeding generations of devices. However, the extra widths required by the above-described landing pads limit the achievable increase in circuit density. For this reason, the excess width accorded to landing pads have been all but eliminated, or at least reduced to less than one nanometer. Such structures, wherein the width of the landing pad is substantially equal to the width of the connected via, are known as “borderless structures”, or “borderless vias”.
The elimination of the extra width of the landing pad makes alignment of the via to the metal line difficult in such borderless vias. During the lithography process, the alignment of the via to the underlying metal line cannot be controlled to less than about ten nanometers misalignment due to inherent tool and processing issues.
FIG. 2
illustrates the results of an inadvertent misalignment between a via
24
and an underlying metal line
26
, resulting in the via
24
being partially disposed outside the borders of the metal line
26
.
FIGS. 3
a
-
3
e
illustrate the steps of an exemplary dual damascene process in which inadvertent misalignment between a via and a metal line occurs. In dual damascene processing, a thin layer
28
(
FIG. 3
a
) of a material having a low dielectric constant K, such as silicon oxide (SiO), is disposed on a semiconductor wafer (not shown). The thickness of the silicon oxide layer
28
can be approximately between 0.5 and 1.0 micrometer. A trench or channel is etched in the silicon oxide layer
28
, and a diffusion barrier layer
30
of tanium/tanium nitride (Ta/TaN) is disposed on the silicon oxide layer
28
. A layer
32
of copper (Cu) is disposed on the barrier layer
30
by electrical plating such that the trench in the oxide layer
28
is filled with copper, and the whole surface of the wafer is covered with copper. The barrier layer
30
prevents the copper from diffusing into the oxide layer
28
.
FIG. 3
b
illustrates the results of a chemical mechanical planarization (CMP) process that removes the copper layer
32
and the barrier layer
30
until the top surface of the oxide layer
28
is reached. The remaining copper layer
32
forms a metal line
33
. An etch stop barrier layer
34
(
FIG. 3
c
) of silicon carbide (SiC) is then disposed on the wafer such that the etch stop barrier layer
34
is substantially planar. The etch stop barrier layer
34
can alternatively be composed of SiO
x
C
y
N
z
, wherein It is possible for any one or two of x, y and z to be zero. That is, the etch stop barrier layer
34
can be composed of SiO
x
C
y
N
z
, SiO
x
C
y
, SiO
x
N
z
, SiC
y
N
z
, SiO
x
, SiC
y
, or SiN
z
.
Next, an intermetal dielectric (IMD) layer
36
(
FIG. 3
d
) of a material having a low dielectric constant K, such as SiO
x
C
y
H
z
, SiOF, SiO
x
, or carbon based film, is disposed over the entire surface of the wafer. The etch stop barrier layer
34
prevents diffusion of the copper from the metal line
33
into the IMD layer
36
.
As illustrated in
FIG. 3
e
, a plug hole is plasma etched in the IMD layer
36
in order to form a via
38
. Due to machine limitations, the via
38
has been inadvertently misaligned with the metal line
33
, as often occurs. The rate of vertical progression of the etch process is slower through the etch stop barrier layer
34
than through the IMD layer
36
because the etch process is designed and optimized for the material composition of the IMD layer
36
. The etch stop barrier layer
34
is over-etched to ensure that all of the etch stop barrier layer
34
is removed from the top surface of the copper metal line
33
, thereby allowing the copper to make good electrical contact with the conductive material to be inserted into the via
38
.
After the etch stop barrier layer
34
has been etched through, the over-etching results in etching of the oxide layer
28
due to the poor selectivity between the etch stop barrier layer
34
and the oxide layer
28
. The etching of the oxide layer
28
results in the formation of a microtrench
40
along the edge of the barrier layer
30
. The rate of etch is faster through the oxide layer
28
than through the etch stop barrier layer
34
, which tends to result in increasing the depth of the microtrench
40
.
The formation of a microtrench
40
is undesirable because it is difficult for chemicals to penetrate into the microtrench
40
. Thus, it is difficult to remove polymer from the microtrench
40
during a solvent cleaning process. It is also difficult to subsequently remove any solvent chemicals that manage to penetrate into the microtrench
40
. Trapped solvent may corrode the metal line
33
. Another problem associated with microtrenching is that the diffusion barrier layer
30
can be etched away from the side of the metal line
33
during the etching process, thereby reducing the reliability of the device. Yet another problem is that a microtrench provides a possible avenue for conductive bridging between adjacent metal lines.
One approach to solving the problems associated with microtrenching is to change the parameters of the etch process, such as gas flows, pressure, temperature and power, in order to improving the selectivity of the etch between the etch stop barrier layer
34
and the oxide layer
28
. However, it has been found that it is difficult to achieve an acceptable level of selectivity because the oxide laye
Eda Masaichi
Elmer Jim
Gu Shiqun
Lin Hong
McGrath Peter
Maginot, Moore & Bowman LLP
Nhu David
LandOfFree
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