Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1998-01-30
2002-03-26
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S041000, C326S047000
Reexamination Certificate
active
06362646
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to programmable logic devices. More specifically, the present invention relates to interconnecting logic and memory elements included within programmable logic devices.
2. Description of the Related Art
A programmable logic device (PLD) is a programmable integrated circuit that allows a user of the circuit, using software control, to program particular logic functions the circuit will perform. Logic functions performed by small, medium, and large-scale integrated circuits can instead be performed by programmable logic devices (PLDS). When an integrated circuit manufacturer supplies a typical PLD, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, can program the PLD to perform particular functions required by the user's application. The PLD then can function in a larger system designed by the user just as though dedicated logic chips were employed. For the purpose of this description, it should be understood that a programmable logic device refers to once programmable devices as well as reprogrammable devices.
Programmable logic encompasses all digital logic circuits that are configured by the end user, including PLDs, field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). The general architecture of the embedded array programmable logic design will be generally familiar to those knowledgeable of the FLEX10K™ logic family of devices manufactured by the Altera Corporation of San Jose, Calif. Such an architecture, for example, is described in U.S. Pat. No. 5,550,782 and Altera Data Book 1996, both of which are incorporated herein by reference.
Referring to
FIG. 1
, a CPLD
100
with a conventional embedded array programmable logic design will be described. Although only a few logic array blocks or memory blocks are illustrated in
FIG. 1
, it should be appreciated that any number may be provided in order to meet the needs of a particular system.
The CPLD
100
includes a core region
102
that couples to vertical bi-directional ports
104
and horizontal bidirectional ports
106
included within a peripheral region
108
. The core region
102
includes a plurality of logic array blocks (LABs)
110
and a plurality of embedded array blocks (EABs)
112
. Each EAB
112
includes an array of memory elements. Each LAB
110
includes a plurality of logic elements (LE) which are capable of performing simple logic functions. An internal logic interconnect included within each LAB serves to interconnect each of the logic elements included therein.
As shown in
FIG. 1
, the plurality of LABs
110
and the plurality of EABs
112
are programmably interconnected by way of global horizontal conductors
114
and global vertical conductors
116
to form a logic and memory array. The global horizontal conductors
114
couple to the horizontal ports
106
and the global vertical conductors
116
couple to the vertical ports
104
.
Additional details of the CPLD
100
are explained with reference to a representative portion
118
of the core region
102
illustrated in FIG.
1
. In the representative portion
118
, the global horizontal conductor
114
-
1
is coupled to EAB
112
-
1
by way of a plurality of local vertical conductors
120
and a plurality of local horizontal conductors
122
. The local vertical conductors
120
are programmably coupled to the global horizontal conductor
114
-
1
by way of a programmable interconnect array (PIA)
124
. The local vertical conductors
120
are also programmably coupled to the local horizontal conductors
122
by way of a programmable interconnect region
126
. The local horizontal conductors
122
in turn couple to the EAB
112
-
1
.
Also, within the representative portion
118
, the global horizontal conductor
114
-
1
is coupled to LAB
110
-
1
by way of a plurality of local vertical conductors
128
and a plurality of local horizontal conductors
130
. The local vertical conductors
128
are programmably coupled to the global horizontal conductor
114
-
1
by way of a programmable interconnect array (PIA)
132
. The local vertical conductors
128
are also programmably coupled to the local horizontal conductors
130
by way of a programmable interconnect region
134
. The local horizontal conductors
130
in turn couple to the LAB
110
-
1
.
In the conventional CPLD
100
architecture, fitting a desired logic function requires various logic elements included in the LAB
110
and/or memory blocks included in the EAB
112
to be individually configured to perform a small but crucial part of the overall logic and/or memory function . Any automatic routing and placing software must then logically connect all the programmed logic elements and/or memory elements such that CPLD
100
can execute the desired logic function and or memory-logic function. Unfortunately, the level of complexity with which the LAB
110
and/or the EAB
112
are to be programmed in order to fit the desired logic function can only be determined when the logic function and/or memory function to be fitted is known. Therefore, in order to have a high probability of successfully fitting a desired logic function and/or memory function, the programmable interconnect array
132
and the programmable interconnect array
124
must each be capable of supplying sufficiently large number I/O signal lines in the form of local vertical conductors so as to be able to support the most complex configurations of the LAB
110
-
1
and the EAB
112
-
1
.
However, most logic functions and/or memory functions do not require the most complex configurations for both the LAB
110
and the EAB
112
in order to be successfully fitted within the CPLD
100
. Therefore, because the programmable interconnect array
132
and the programmable interconnect array
124
are designed to handle worse case conditions, the programmable interconnect arrays
124
and
132
typically include far more programming resources in the form of programmable connectors than is needed to successfully fit a logic function. This results in inefficient use of programming resources which unnecessarily increases the quantity of memory cells
162
required to fit complex logic functions.
By way of example, the LAB
110
-
1
is capable of being programmed to perform a logic function that requires, for example, a quantity M of I/O signals carried by a quantity M of local horizontal conductors
130
. Each of the quantity M of local horizontal conductors
130
in turn must be capable of carrying a separate I/O signal that originates from an associated one of a quantity N of row channels included in the global horizontal conductor
114
-
1
, for example. Therefore, the quantity M of local horizontal conductors
130
requires a quantity M of local vertical conductors
128
each having at least an associated quantity N of programmable connectors.
In a similar fashion, the EAB
112
-
1
is capable of being programmed to perform a logic/memory function that requires, for example, a quantity of R I/O signals carried by a quantity R of local horizontal conductors
122
. Each of the quantity of R local horizontal conductors
122
in turn must be capable of carrying a separate I/O signal that originates from an associated one of a quantity N of row channels included in the global horizontal conductor
114
-
1
, for example. Therefore, the quantity R of local horizontal conductors
122
requires a quantity R of local vertical conductors each having at least an associated quantity N of programmable connectors.
Therefore, if the CPLD
100
includes a quantity &mgr;
1
of LABs
110
and a quantity &mgr;
2
of EABs
112
, a quantity T of memory cells
162
need is determined by the following equation,
T=(&mgr;
1
×M×N)+(&mgr;
2
×R×N).
Hence, the amount of memory cells
162
that must be necessarily included in the CPLD
100
in order to assure a high probability
Altera Corporation
Beyer Weaver & Thomas LLP
Cho James A.
Tokar Michael
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