Method and apparatus for reducing memory latency in a cache...

Details Method and apparatus for reducing memory latency in a cache... Method and apparatus for reducing memory latency in a cache...

2007-06-19

2007-06-19

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S100000, C711S141000, C711S146000

Reexamination Certificate

active

09749660

ABSTRACT:
A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.

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