Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2006-01-03
2006-01-03
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S320000, C711S145000
Reexamination Certificate
active
06983388
ABSTRACT:
A method and apparatus are disclosed for reducing leakage power in a cache memory. A cache decay technique is employed for both data and instruction caches that removes power from cache lines that have not been accessed for a predefined time interval, referred to as the decay interval. The cache-line granularity of the present invention permits a significant reduction in leakage power while at the same time preserving much of the performance of the cache. The decay interval is maintained using a timer that is reset each time the corresponding cache line is accessed. The decay interval may be fixed or variable. Once the decay interval timer exceeds a specified decay interval, power to the cache line is removed. Once power to the cache line is removed, the contents of the data and tag fields are allowed to decay and the valid bit associated with the cache line is reset. When a cache line is later accessed after being powered down by the present invention, a cache miss is incurred while the cache line is again powered up and the data is obtained from the next level of the memory hierarchy.
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Diodato Philip W.
Kaxiras Stefanos
McLellan, Jr. Hubert Rae
Narlikar Girija
Agere Systems Inc.
Cao Chun
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