Method and apparatus for reducing interrupt latency by...

Details Method and apparatus for reducing interrupt latency by... Method and apparatus for reducing interrupt latency by...

2005-12-13

2005-12-13

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S056000

Reexamination Certificate

active

06976110

ABSTRACT:
A method for reducing interrupt latency in a data processing system wherein a storage device is provided having a predetermined maximum number of storage locations. Data execution circuitry is coupled to the storage device for providing data to the storage device and storing the data in the storage device. Interrupt control circuitry is coupled to the data execution circuitry, wherein the interrupt control circuitry interrupts the data execution circuitry. The data stored in the storage device is completely outputted, thereby having an associated interrupt latency resulting from the output of the stored data. The storage capacity of the storage device is changed dynamically to minimize the interrupt latency. The storage device has a utilization value that varies between a predetermined minimum number of storage locations and the predetermined maximum number of storage locations based upon an operating mode of the data processing system.

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“System level performance analysis—the SymTA/S approach” by Henia et al. (abstract only) Publication Date: Mar. 2005.
Related Application, U.S. Appl. No. 10/322,313, filed Dec. 18, 2002.

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