Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-05-03
2002-03-05
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S750000, C257S758000
Reexamination Certificate
active
06353261
ABSTRACT:
TECHNICAL FIELD
The field of the present invention pertains to Integrated Circuit (IC) fabrication. More particularly, the present invention relates to the field of interconnect lines for an IC.
BACKGROUND ART
ICs use layers of semiconductor material, insulator material, and conductor material to build up integrated circuit patterns. Today's integrated circuits typically have multiple two-dimensional circuits layered on top of each other in a third dimension and separated by a dielectric layer. The different layers within the multilayered IC are formed by vapor deposition, electroplating, or other traditional means. Components, such as diodes, resistors, transistors, etc. are formed in these layers and are coupled together by interconnect lines
Referring to Prior Art
FIG. 1A
, a top view of a prior art multilayered IC
100
, is shown. Similarly, Prior Art
FIG. 1B
presents a view of several cross-sections taken from the top view of the prior art multilayered IC
100
. Multilayered IC
100
is comprised of a first circuit layer
102
and a second circuit layer
106
separated by a layer
104
made of dielectric material
103
to prevent shorting across two layers of circuits
102
and
106
. Interconnect line
108
is formed in a dielectric material
103
in first circuit layer
102
to couple components in first circuit layer
102
that are not shown in the figure. Similarly, interconnect lines
112
and
114
exist in second circuit layer
106
. While line
114
in second circuit layer
106
and line
108
in first circuit layer
102
are separated by layer
104
of dielectric material
103
, as shown in Section A—A, line
112
in second circuit layer
106
and line
108
in first circuit layer
102
do connect, as shown in Section C—C. The connection is part of the circuit design that requires communication between different circuit layers, e.g. layer
102
and layer
106
, at a specific point. The connection is made by an interconnect referred to as a ‘via’
110
. The via contact
110
consequently forms a threedimensional circuit within the multilayered IC.
As is typical with ICs, there is a demand for faster operating speed in the circuit. The speed of the circuit is limited by, among other things, the delay of a component in the circuit and the delay of the interconnects communicating a signal between multiple components and leads. The delay of the components have been reduced so greatly in modern circuits, that the delay of the interconnects is now becoming a limiting factor in the overall speed of the IC. Consequently, a need arises for an apparatus and a method to decrease the delay of the interconnects in an IC so as to increase the overall speed of the IC.
The delay of the interconnect is described by its time constant, &tgr;=RC, where R is the resistance, in ohms, of a circuit and C is the capacitance, in farads, of the circuit. Conventional improvements to reducing the time constant include the use of low “k” materials to reduce capacitance and the use of electroplated bulk copper for interconnects to reduce resistance. The “k” value refers to the inherent capacitance of a given material based on its permittivity, e.g. k=1/(4&pgr;*t*∈), where ∈ is the permittivity of the material in farads/meter. However, additional improvements beyond the use of low k materials are still necessary. Hence, a need exists for an apparatus and method to reduce the resistance of interconnects in an IC.
The resistance of an interconnect is described by the resistivity equation:
R=(&rgr;*
1)/
A.
In this equation, R is the resistance in ohms, or voltseconds/coulomb, &rgr;=resistivity of the material in CM-ohms/ foot, l=length of the conductor in feet, and A is the cross-sectional area of the conductor in circular mils (CM). By viewing the equation, it is apparent that the resistance of a conductor can be decreased by changing any of the variables in the correct direction. As an example, the resistance of the conductor can be reduced by increasing the cross-sectional area, A, of the conductor. However, most ICs have a thickness requirement and an interconnect width requirement that must be satisfied.
Consequently, a need arises for an apparatus and a method that reduces the resistance of an interconnect while maintaining the standard thickness of a circuit layer and a given width of an interconnect line in a multilayer IC.
In summary, a need exists for an apparatus and a method to decrease the delay of the interconnects in an IC so as to increase the overall speed of the IC. To satisfy this goal, a need exists for an apparatus and method to reduce the resistance of interconnects in an IC. More specifically, a need arises for an apparatus and a method to reduce the resistance of an interconnect while maintaining the standard thickness of a layer and a given width of an interconnect line in a multilayer IC.
DISCLOSURE OF THE INVENTION
The present invention provides an apparatus and a method that decreases the delay of the interconnects in an IC so as to increase the overall speed of the IC. The present invention reduces the delay of an interconnect by reducing the resistance of interconnects by increasing the cross-sectional area of the interconnect while maintaining the standard thickness of layers in a multilayer IC and a given width of the interconnect. The present invention uses, in essence, a free cross-sectional area not being used by any other component in the IC.
One embodiment of the present invention increases the cross-sectional area of the interconnect by adding an interconnect well in the multi-layered IC, during fabrication, that is in direct contact with the interconnect line. By increasing the cross-sectional area of the interconnect, the resistance is decreased and consequently, the delay of the interconnect is reduced. The interconnect well can be located between an interconnect line in a first circuit layer and a bottom surface a second circuit layer meeting the following conditions. The second circuit layer design has an insulative material in an area approximately overlaying the interconnect line and the material between the second circuit layer and the interconnect line is designed to be an insulative material. The design referred to is the baseline design of the IC with conventional interconnects. With the addition of an interconnect well, the baseline design becomes a modified design with reduced interconnect delay and other improvements.
In areas where proximate circuit layers of an IC have overlapping interconnects, there is usually insufficient insulative material between the sequential layers of ICs for an interconnect well. This is usually true regardless of whether overlapping interconnect lines in sequential layers are insulated from each other or are coupled to each other. The thickness of insulation provided between adjacent circuit layers is provided to satisfy insulative requirements, e.g. no shorting, and to satisfy capacitive interactions between components in each layer.
However, many areas of the IC have no overlapping interconnects in proximate circuit layers. The result is usually an excess area of insulative material in the multi-layer IC proximate to at least a portion of an interconnect. The present invention creates an interconnect well where the large areas of insulative material exist in the multi-layer IC. The present invention capitalizes on this essentially component-free area of excess insulative material to increase the cross-sectional area of the interconnect line, and consequently reduce its resistance and its delay. The interconnect well probably will not exist for the entire length of an interconnect line because of an interconnect lines existing at intermittent locations in proximate circuit layers that would prohibit the use of an interconnect well at that specific location. Notwithstanding this fact, the present invention still provides a decrease in at least a portion of the length of an interconnect line, and thus, provides at least some reduction in the delay of the interconnec
Clark Jhihan B
Lee Eddie
VLSI Technology Inc.
Wagner , Murabito & Hao LLP
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