Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-11-03
2003-09-02
Shin, Christopher B. (Department: 2782)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S107000, C710S112000, C710S005000, C710S027000, C710S036000
Reexamination Certificate
active
06615306
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of computer systems and more specifically to optimizing flow of information between components in computer systems.
2. Description of the Related Art
Prior art systems often use a configuration of components as illustrated in FIG.
1
. CPU
101
(a Central Processor or Processor) is coupled through a Processor Bus
102
to a component referred to as a Host Bridge
105
, and thereby coupled to the rest of the system. Host Bridge
105
is coupled to Memory
103
, the main memory of the system, and Host Bridge
105
is also coupled to I/O Bridge
107
(Input/Output Bridge). I/O Bridge
107
couples to Keyboard
109
, Mouse
111
, and Disk Drive
110
, and may couple to other components in a bus or point-to-point fashion. Through these couplings, CPU
101
is coupled to each component in the system, and may read or write information to each of the devices (within the capabilities of those devices).
Further extending the complexity of the system, PCI Bus
125
(Peripheral Component Interconnect Bus based on the Peripheral Component Interconnect Bus Specification Revision 2.1 or 2.2 from the Portland PCI Working Group as published by Intel Corporation) may be involved in the coupling of Host Bridge
105
to I/O Bridge
107
, and may thereby couple PCI Agents
120
, other devices on the PCI Bus
125
. Thus, through Host Bridge
105
, CPU
101
may communicate with PCI Agents
120
. While it is advantageous to make PCI Agents
120
available to the system, incorporating the PCI Bus
125
into a coupling or connection between two components further complicates the physical devices and layout, and the protocols for communication over that coupling.
SUMMARY OF THE INVENTION
A method and apparatus for reducing flow control and minimizing interface acquisition latency in a hub interface is a method of transferring data between a control hub coupled to a hub interface which is coupled to an input-output hub including the following: Transferring the data in packets. Prioritizing isochronous transfers over asynchronous transfers. Limiting asynchronous transfers to 32 bytes per packet when an agent requests the hub interface, and limiting asynchronous transfers to 64 bytes per packet when no requests for the hub interface are recognized.
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Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Shin Christopher B.
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