Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-10-24
2003-05-13
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C438S659000
Reexamination Certificate
active
06563222
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor fabrication, and more particularly to methods for reducing the electromigration of copper at interconnect-via interfaces in semiconductor devices such as very- and ultra-large scale integration (VLSI/ULSI) devices.
BACKGROUND OF THE INVENTION
Semiconductor chips or wafers are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
Accordingly, a single chip can contain a large number of electrical circuit components, including transistors. As will be readily appreciated, the circuit components of a chip must be electrically connected to other components to establish an electrical circuit. With this in mind, very small electrical leads, referred to as “interconnects,” are used to electrically connect circuit components to other appropriate circuit components and devices. As part of establishing electrical contact between an, interconnect and, for example, a transistor having a source and drain embedded in a dielectric material, a channel is formed through the dielectric material for each source and drain. The channel is filled with a conductor referred to as “via,” with the interconnects then disposed in contact with the vias to establish proper electrical communication with the transistor.
As recognized by the present invention, when an interconnect is made of copper, electromigration of copper atoms from the interconnect into the via can occur. This can result in the formation of voids at the via-interconnect interface, which undesirably reduces the performance of the circuit by increasing the electrical resistance at the interface. As further recognized herein, the above-described electromigration can be reduced by doping the copper interconnects with impurities, but the impurities in turn can undesirably increase the resistance of the copper interconnect. Fortunately, the present invention addresses the problem of reducing electromigration at via-interconnect interfaces while minimizing the resistance of the interconnect.
BRIEF SUMMARY OF THE INVENTION
A method is disclosed for establishing an electrical connection to a circuit component in a semiconductor device. The method includes disposing a portion of an interconnect adjacent a circuit component location, and doping the portion of the interconnect with an impurity to establish a doped portion. Then, electrical contact is established between the doped portion of the interconnect and the circuit component. The impurity can be selected from the group including: Palladium (Pd), Zirconium (Zr), Tin (Sn), Magnesium (Mg), and Scandium (Sc).
In a preferred embodiment, the device includes a layer of dielectric material. In this preferred embodiment, the method further includes forming a channel through the dielectric material, and directing the impurity through the channel into the interconnect such that the impurity is implanted into the interconnect. The impurity can be implanted using ion implantation, plasma enhanced deposition, or thermal diffusion. An electrically conductive via material is then disposed in the channel for establishing electrical contact between the doped portion of the interconnect and the circuit component (e.g., the source or drain of a transistor). A semiconductor device made according to the present method, as well as a digital processing apparatus incorporating the device, are also disclosed.
In another aspect, a method for making a large scale integration semiconductor device includes arranging plural circuit components on a substrate, and also arranging plural interconnects adjacent the circuit components. At least some interconnects have doped portions and undoped portions. The method further contemplates establishing electrical contact between at least some of the doped portions of the interconnects and at least some of the circuit components.
In still another aspect, a semiconductor device includes a circuit component including at least one via, and an interconnect having at least one doped portion disposed entirely beneath the via in electrical contact therewith. Portions of the interconnect that are contiguous to the doped portion are not doped. Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION.”
REFERENCES:
patent: 4907066 (1990-03-01), Thomas
patent: 5633199 (1997-05-01), Fiordalice et al.
patent: 5646448 (1997-07-01), Klein et al.
patent: 5654245 (1997-08-01), Allen
patent: 6306732 (2001-10-01), Brown
Lopatin Sergey
Nogami Takeshi
Advanced Micro Devices , Inc.
Hoang Quoc
LaRiviere Grubman & Payne, LLP
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