Static information storage and retrieval – Read/write circuit – Complementing/balancing
Reexamination Certificate
2000-08-16
2002-03-12
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Complementing/balancing
C365S203000, C365S189050
Reexamination Certificate
active
06356492
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to reducing the current drain in a memory device caused by row to column shorts.
DISCUSSION OF THE RELATED ART
As cell density of memory devices, e.g., DRAM devices, continues to increase, there is a corresponding need to reduce the amount of current drawn by such devices. One source of undesired current draw is row to column shorts. Increasing cell density also increases the number of row to column shorts which may be present in a memory device. If too much current is consumed by row to column shorts, a memory device will not meet strict specifications required for its voltage source, standby current, and self-refresh current.
One solution for dealing with row to column shorts is illustrated in FIG.
1
.
FIG. 1
illustrates an equilibrate circuit
29
which is typically provided across the complementary digit lines
11
and
13
of a column of a memory device. The equilibrate circuit
29
includes a transistor
23
which is designed to couple the digit lines
11
and
13
together during an equilibrate operation, and a pair of transistors
25
and
27
which provide a voltage from a node A to the respective digit lines
11
and
13
. The voltage at node A is in turn supplied through a transistor
35
which has a source coupled to a voltage potential, which is typically equal to half the supply voltage Vcc, that is Vcc/2.
The gate of transistor
35
is coupled to a charge pump output voltage Vccp which causes transistor
35
to continuously supply the voltage Vcc/2 to node A during normal operation of a device. The equilibrate circuit
29
is activated in response to an equilibrate control signal EQ on the equilibrate line
31
to turn on transistors
23
,
25
and
27
. Equilibration of the digit lines
11
and
13
is performed just prior to a read operation by sense amplifier
37
, which is also coupled to the complementary digit lines
11
and
13
.
A word line
15
is also illustrated in
FIG. 1
, which coupled to a gate of a memory cell access transistor
17
which serves to read out charge stored in a cell capacitor
19
. A short between a row line
15
and column (digit) line
13
is illustrated as a resistance
21
in FIG.
1
. During the equilibration operation word line
15
is grounded. Accordingly, a row to column
21
short will cause a current drain in the path from node A through transistor
27
, digit line
13
, and word line
15
during the equilibration operation.
In order to limit current when a row to column short exists, the transistor
35
is provided with a relatively long current limiting N-channel, as depicted in
FIGS. 2 and 3
.
FIG. 2
is a sectional side view showing the source and drain regions of transistor
35
and the long channel L, while
FIG. 3
illustrates a top view of the long channel L. In one typical arrangement, the width to length of the channel region of transistor
35
is 2.6/19 as shown in FIG.
3
.
While the long N-channel does serve to limit current in case of a row to column short to typically 40 uA as the number of row to column shorts increases in different columns of high density memory devices, this conventional technique begins to draw increasing amounts of current, thus hindering the ability of memory device to meet tight voltage and current specifications.
In this regard, it should be noted that while the
FIG. 1
circuit shows a long channel transistor
35
connected to a single equilibrate circuit
29
, in actual practice transistor
35
is connected to a plurality of equilibrate circuits
29
in a column of a memory device.
As a consequence, as densities of memory devices increase with corresponding increases in row to column shorts, there is a need for an improved circuit for supplying Vcc/2 to the equilibrate circuit
29
which does not consume large amounts of current in the presence of row to column shorts.
SUMMARY OF THE INVENTION
The present invention overcomes the problem with the
FIG. 1
circuit by substituting the transistor
35
with a latch circuit which supplies voltage Vcc/2 to one or more equilibrate circuits
29
, as long as the current drawn from the latch circuit is below a predetermined threshold. Once the drawn current exceeds the predetermined threshold, the latch circuit switches to a state where voltage is no longer supplied to the equilibrate circuits.
Preferably, the latch circuit is a self-switching circuit, so that as soon as the current drawn from the latch exceeds the predetermined threshold current, the latch self switches to the state where no voltage is supplied to the equilibrate circuits.
REFERENCES:
patent: 5881002 (1999-03-01), Hamakawa
patent: 5896334 (1999-04-01), Casper
Dickstein , Shapiro, Morin & Oshinsky, LLP
Zarabian A.
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