Static information storage and retrieval – Read/write circuit – Signals
Patent
1997-03-13
1999-01-26
Hoang, Huan
Static information storage and retrieval
Read/write circuit
Signals
36518901, 36518908, G11C 700
Patent
active
058645098
ABSTRACT:
The present invention significantly lowers the continuous write cycle ICC, thus lowering the overall ICC specification, for multi-port (and single port) memory devices without significant changes in ICC.sub.WR and ICC.sub.RR currents. In one embodiment, a circuit for the generation of a Write Data select signal (i.e., TTL.sub.-- SEL) according to the present invention employs a unique "write power-down" delay (t.sub.WPD) which is a function of "CE+WE" (chip select and write enable) and incorporates the delay into the generation of the Write Data select signal, TTL.sub.-- SEL. The delay t.sub.WPD is provided by a delay device and is preferential. That is, a delay is provided when the internal write data select signal, i.e., TTL.sub.-- sel (which is a function of "CE+WE"), transitions from logic "1" to a logic "0", but no delay is produced when TTL.sub.-- sel transitions from a logic "0" to a logic "1".
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patent: 5590088 (1996-12-01), Sakurada
Cypress Semiconductor Corp.
Hoang Huan
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