Method and apparatus for reducing clock skew in an...

Details Method and apparatus for reducing clock skew in an... Method and apparatus for reducing clock skew in an...

2005-10-25

2005-10-25

Du, Thuan (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000, C713S503000

Reexamination Certificate

active

06959396

ABSTRACT:
A method is provided to reduce clock skew in an integrated circuit having a number of circuit blocks, which comprises the following steps. A first source clock coupled to a clock input terminal of a first circuit block within the circuit blocks is provided, as is a second source clock coupled to a clock input terminal of a second circuit block within the circuit blocks. When the second circuit block is configured to operate in synchronization with the first circuit block, the clock input terminal of the second circuit block is switched to the first source clock, and thus both the first circuit block and the second circuit block can operate in accordance with the same first source clock.

REFERENCES:
patent: 5274678 (1993-12-01), Ferolito et al.
patent: 5483185 (1996-01-01), Scriber et al.
patent: 5517638 (1996-05-01), Szczepanek
patent: 5758132 (1998-05-01), Strahlin
patent: 5758136 (1998-05-01), Carlson
patent: 5774699 (1998-06-01), Nagae
patent: 6516422 (2003-02-01), Doblar et al.

Affiliated with

Also associated with

Rating

Method and apparatus for reducing clock skew in an... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for reducing clock skew in an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing clock skew in an... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3489376