Method and apparatus for reducing cache thrashing

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S128000, C711S209000

Reexamination Certificate

active

06874056

ABSTRACT:
A method and apparatus are disclosed for adaptively decreasing cache trashing in a cache memory device. Cache performance is improved by automatically detecting thrashing of a set and then providing one or more augmentation frames as additional cache space. In one embodiment, the augmentation frames are obtained by mapping the blocks that map to a thrashed set to one or more additional, less utilized sets. The disclosed cache thrashing reduction system initially identifies a set that is likely to be experiencing thrashing, referred to herein as a thrashed set. Once thrashing is detected, the cache thrashing reduction system selects one or more additional sets to augment a thrashed set, referred to herein as the augmentation sets. In this manner, blocks of main memory that are mapped to a thrashed set are now mapped to an expanded group of sets (the thrashed set and the augmentation sets). Finally, when the augmentation sets are no longer likely to be needed to decrease thrashing, the augmentation set(s) are disassociated from the thrashed set(s).

REFERENCES:
patent: 5630097 (1997-05-01), Orbits et al.
patent: 5752261 (1998-05-01), Cochcroft, Jr.
patent: 6115793 (2000-09-01), Gruber et al.
patent: 6154812 (2000-11-01), Hetherington et al.
patent: 6625695 (2003-09-01), Fanning
patent: 20020099912 (2002-07-01), Nakamura et al.
Kaxiras et al, “Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power,” IEEE, (2001).
Lai et al., “Dead-Block Prediction & Dead-Block Correlating Prefetchers,” IEEE, (2001).
Mendelson et al, “Modeling Live and Dead Lines in Cache Memory System,” IEEE, Trans. on Computers, v. 42, No. 1, (Jan. 1993).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for reducing cache thrashing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for reducing cache thrashing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing cache thrashing will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3370606

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.