Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt inhibiting or masking
Reexamination Certificate
1998-06-23
2001-09-18
Sheikh, Ayaz R. (Department: 2781)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt inhibiting or masking
C710S120000, C710S120000, C710S200000
Reexamination Certificate
active
06292865
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to data transfers in a computer system. More particularly, this invention relates to transferring data between two buses in a computer system using a bus bridge.
2. Background
As technology has progressed, the number, types, and functional power of computer system components has steadily increased. Given the large number and different operating speeds of different components, modem computer systems typically include two, three, or more buses for coupling together the different components.
One device commonly used to couple together two buses is referred to as a bus bridge. Typically, requests transferred between buses via a bus bridge can be either posted or non-posted. A posted request refers to a request from a source agent on a source bus which has been accepted by the bridge, and the source agent knows that the request will be provided to the target agent on the target bus, regardless of whether the request has been actually delivered to the target agent yet or whether it is pending in a buffer in the bridge. A non-posted request refers to a request which is being transferred through the bus bridge and the source agent does not know whether the request can be delivered to the target agent until it is actually received by the target agent.
One important goal in designing a bus bridge is to provide an efficient communication path between the two buses. However, one problem that can arise when using a bus bridge is referred to as “thrashing”. Thrashing refers to a situation where both of the buses are fully utilized, but very few, if any, data transfers between the two buses can progress. This situation can arise, for example, in a system having a bus bridge coupling a system bus and a Peripheral Component Interconnect (PCI) bus, such as a bus in accordance with the PCI Local Bus Specification, Version 2.0, published Apr. 30, 1993, or Version 2.1, published Jun. 1, 1995. If an agent on the PCI bus is writing to main memory on the system bus and posting in the bus bridge is disabled, then if a processor on the system bus is repetitively issuing requests targeting the PCI bus, each of the requests outstanding on the buses can prevent the requests of the other from progressing. When thrashing occurs, data transfers between the two buses cannot be made. Furthermore, the requests which are causing the thrashing to occur may also lock up the two buses such that no other requests can be issued by other agents on those buses. It would be beneficial to provide a mechanism which reduces thrashing in a computer system.
An additional problem which can arise when using a bus bridge is referred to as “livelock”. A livelock condition refers to a thrashing condition that persists indefinitely. Given the indefinite duration, the livelock can lock up the computer system for an indefinite period of time. It would be beneficial to provide a mechanism which reduces livelock in a computer system.
Another problem which can arise when using a bus bridge is referred to as read starvation. Read starvation of a PCI bus master, for example, can occur if the PCI bus master is not able to get through to the system bus because of requests from system bus masters. Read starvation can result in poor system performance, due to the inability of the PCI bus master to perform its tasks. It would be beneficial to provide a mechanism which reduces read starvation in a computer system.
As will be described in more detail below, the present invention provides a method and apparatus for masking processor requests to achieve these and other desired results which will be apparent to those skilled in the art from the description that follows.
SUMMARY OF THE INVENTION
A method and apparatus for masking processor requests to improve bus efficiency is described herein. A bus bridge includes a detection logic to determine when a first processor on a first bus has been backed off the first bus a predetermined number of times. When the detection logic determines the first processor has been backed off the first bus the predetermined number of times, a timer is set to a first value sufficient to allow an agent on a second bus to access the first bus. A masking logic, coupled to the detection logic and the timer, masks requests from the first processor until the timer expires.
Additionally, in one embodiment of the present invention, a sensing logic monitors PCI master requests for the first bus. If the sensing logic senses that no PCI master requests for the first bus have occurred for a period of time, the processor is unmasked and the timer is cleared.
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Congdon Bradford B.
McTague Michael J.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Sheikh Ayaz R.
Thlang Eric S.
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