Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-11-01
2005-11-01
Tran, Denise (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S154000
Reexamination Certificate
active
06961819
ABSTRACT:
A method and apparatus within a processing system is provided for separating access to an instruction memory and a data memory to allow concurrent access by different pipeline stages within the processing system to both the instruction memory and the data memory. An instruction memory interface is provided to access the instruction memory. A data memory interface is provided to access the data memory. Redirection logic is provided to determine whether an access by the data memory interface should be directed to the instruction memory interface utilizing either the address of the access, or the type of instruction that is executing.
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Intrater Gideon D.
Jagd Anders M.
Kinter Ryan C.
Huffman James W.
MIPS Technologies Inc.
Tran Denise
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