Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2011-03-22
2011-03-22
Suryawanshi, Suresh K (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S500000, C713S400000
Reexamination Certificate
active
07913104
ABSTRACT:
Data and clock synchronization within a gigabit receiver is maintained throughout the data byte processing logic of the receiver by utilizing the same byte clock signal. The deserialization clock signal that is used to deserialize the received serial data stream is phase coherent with the distributed byte clock signal used within the physical coding sublayer (PCS), thus establishing reliable data transfer across the physical media attachment (PMA) and PCS layers of the gigabit receiver while maintaining a known, fixed latency. The phase relationship between a derived bit clock signal and the byte clock signal is shifted in a manner that achieves coarse data alignment within each data byte without affecting the latency. Conversely, the coarse data alignment is combined with a data alignment toggling procedure to reduce data alignment granularity with minimized latency changes.
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U.S. Appl. No. 11/040,423, filed Jan. 21, 2005, Davidson, Scott Allen et al., “Method and Apparatus for Providing Clocking Phase Alignment in a Transceiver System” 37 pages, available from Xilinx, 2100 Logic Drive, San Jose, California 95124.
Cory Warren E.
Liu Dean
Portmann Clemenz
Stark Donald
King John J.
NetLogic Microsystems, Inc.
Suryawanshi Suresh K
Wallace Michael T.
Xilinx , Inc.
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