Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-11-17
2001-05-29
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C365S201000
Reexamination Certificate
active
06240525
ABSTRACT:
BACKGROUND
1. Field of Invention
This invention relates generally to semiconductor memories and specifically to semiconductor memories having one or more defective cells.
2. Description of Related Art
Modern semiconductor memory devices such as, for instance, SRAM, DRAM, EEPROM, and Flash Memory, store millions of bits of information on a single chip. These memory devices require at least one transistor per memory cell, in addition to the thousands of transistors required for peripheral logic functions, e.g., row and column decoders, sense amps, and so on. Thus, even when manufactured using state of the art wafer fabrication technology, a one Megabyte semiconductor memory device may include hundreds or even thousands of defective cells. Additional memory cells may become defective during operation of such semiconductor memories. Although numerous well known redundancy techniques are available to repair defective memory cells, implementation of such techniques consumes considerable silicon area and is therefore typically impractical where die size is of primary concern.
The extent to which defective memory cells affect computer performance depends in part upon the particular application for which the semiconductor memory is used. For instance, since video data is relatively static, i.e., adjacent pixel information is often identical, the presence of one or two defective cells in a common row i.e., page, of memory has a minimal effect upon the resultant video image. However, where all bit information is vital, e.g., when storing encryption key information, the presence of even one defective cell can significantly degrade performance.
Application-Specific Integrated Circuits (ASIC) are well known and typically include an on-chip semiconductor memory. ASICs are used in a wide variety of applications ranging from cellular phones to dishwashers to DVD players and typically perform vital functions for their hosts, e.g., a DVD player. When some of the memory cells of an ASIC become defective during operation, the corresponding page of the memory becomes unusable. In some applications, a defective page may render the entire memory defective and, therefore, render the ASIC useless. Since, as described above, cell redundancy circuitry is often not feasible, there is a need to compensate for defective memory cells while sustaining normal ASIC operation, and without consuming additional silicon area.
SUMMARY
A method and apparatus are disclosed which prevent defective memory cells from corrupting an entire memory array. In accordance with the present invention, a semiconductor memory array is partitioned into a predetermined number of sections. A first register stores dynamic values indicative of whether corresponding cells of the memory are defective, and includes an input terminal coupled to receive addresses from an associated address generator. A second register stores address mappings of corresponding cells in each of the partitioned sections, and includes an input terminal coupled to receive addresses from the address generator. A multiplexer includes first and second input terminals coupled to receive addresses from the address generator and mapped address from the second register, respectively, a control terminal coupled to receive the dynamic values from the first register, and an output terminal coupled to the address input lines of the memory array. When the address generator provides an address in response to a request from an associated CPU, the first register indicates whether the memory location addressed by the request is defective. If the corresponding memory cell is not defective, information is read from or written to the corresponding memory cell as normal. If, on the other hand, the corresponding memory cell is defective, the information is re-addressed to a corresponding cell of another partitioned section of the memory according to the address mapping provided by the second register. In some embodiments, a page of memory associated with the defective cell is re-addressed to a corresponding page in another partitioned section.
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Iqbal Nadeem
Oak Technology, Inc.
Paradice III William L.
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