Computer graphics processing and selective visual display system – Computer graphics display memory system – Frame buffer
Reexamination Certificate
2006-05-09
2006-05-09
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Frame buffer
C345S564000, C345S531000
Reexamination Certificate
active
07042460
ABSTRACT:
A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile hierarchy. For this hierarchy, smaller low-level tiles combine to form larger mid-level tiles. Mid-level tiles combine to form high-level tiles. The tile hierarchy may be expanded to include more levels, or collapsed to included fewer levels. A graphics primitive is rasterized by selecting an starting vertex. The low-level tile that includes the starting vertex is then rasterized. The remaining low-level tiles that are included in the same mid-level tile as the starting vertex are then rasterized. Rasterization continues with the mid-level tiles that are included in the same high-level tile as the starting vertex. These mid-level tiles are rasterized by rasterizing their component low-level tiles. The rasterization process proceeds bottom-up completing at each lower level before completing at higher levels. In this way, the present invention provides a method for rasterizing graphics primitives that accesses memory tiles in an orderly fashion. This reduces page misses within the frame buffer and enhances graphics performance.
REFERENCES:
patent: 4780709 (1988-10-01), Randall
patent: 5226175 (1993-07-01), Deutsch et al.
patent: 5251296 (1993-10-01), Rhoden et al.
patent: 5321809 (1994-06-01), Aranda
patent: 5471248 (1995-11-01), Bhargava et al.
patent: 5598517 (1997-01-01), Watkins
patent: 5729672 (1998-03-01), Ashton
patent: 5815168 (1998-09-01), May
patent: 5852443 (1998-12-01), Kenworthy
patent: 5977977 (1999-11-01), Kajiya et al.
patent: 5982384 (1999-11-01), Prouty et al.
patent: 5990912 (1999-11-01), Swanson
patent: 6111583 (2000-08-01), Yaron et al.
patent: 6144392 (2000-11-01), Rogers
patent: 6215507 (2001-04-01), Nally et al.
patent: 6246415 (2001-06-01), Grossman et al.
patent: 6433782 (2002-08-01), Nakatsuka et al.
patent: 0 447 225 (1991-09-01), None
Juan Pineda. A Parallel Algorithm for Polygon Rasterization. In Computer Graphics, vol. 22, No. 4, Aug. 1988, p. 17-20.
Greene, N., “Hierarchical Polygon tiling with Coverage Masks”,Proceedings of the 23rdAnnual Conference on Computer Graphics, 1996, 65-74.
McCormack, J. et al., “Neon: A Single-Chip 3D Workstation Graphics Accelerator”,Proceedings of the 1998 Eurographics/SIGGRAPH Workshop.
Montrym, J. et al., “InfiniteReality: A Real-Time Graphics System”,Proceedings of the 24thAnnual Conference on Computer Graphics&Interactive Techniques, 1997, 293-302.
Hussain Zahid S.
Millet Timothy J.
Microsoft Corporation
Tung Kee M.
Woodcock & Washburn LLP
LandOfFree
Method and apparatus for rasterizing in a hierarchical tile... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for rasterizing in a hierarchical tile..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for rasterizing in a hierarchical tile... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3568766