Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-12-22
2000-06-20
Gulakowski, Randy
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438694, 438906, 438972, H01L 213205
Patent
active
060777621
ABSTRACT:
Disclosed is a method for making reliable interconnect structures on a semiconductor substrate having a first dielectric layer. The method includes plasma patterning a first metallization layer that lies over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer. The method further includes contacting the second metallization layer with a conductive liquid that is electrically grounded. In this manner, the positive charge that is built-up on the at least part of the second metallization layer is neutralized to prevent tungsten plug erosion.
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Bothra Subhas
Liang Victor C.
Sur, Jr. Harlan Lee
Gulakowski Randy
Olsen Allan
VLSI Technology Inc.
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