Method and apparatus for rapid computation of target addresses f

Details Method and apparatus for rapid computation of target addresses f Method and apparatus for rapid computation of target addresses f

1997-10-22

1999-01-12

Lee, Thomas C.

Electrical computers and digital processing systems: memory

Address formation

Generating prefetch, look-ahead, jump, or predictive address

395586, G06F 932

Patent

active

058601520

ABSTRACT:
A method and apparatus accepts a relative control transfer instruction and generates a compact absolute control transfer instruction which may have a number of bits one greater than the relative control transfer instruction and including flags to rapidly construct the target address of the relative control transfer instruction. The compact absolute control transfer instruction is generated by sign extending the displacement of the relative control transfer instructions and adding it to a set of least significant bits from the control transfer instruction address, and optionally coupling some or all of the bits from the result with the original opcode or a different opcode. The target address of the relative control transfer instruction is determined by using, incrementing or decrementing, depending on the state of the flags, a group of the most significant bits from the relative control transfer instruction address and appending the result with the least significant bits from the result of the addition described above.

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Bernard K. Gunther, "A High Speed Mechanism for Short Branches", Computer Architecture News, Dec. 1990, vol. 18, No. 4, pp. 59-61.

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