Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1998-06-24
2001-07-17
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S104000, C713S001000, C714S028000
Reexamination Certificate
active
06263412
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory in processor-based or microcontroller-based systems, and more particularly, to an apparatus and method of emulating random access memory using a processor register set.
2. Description of the Related Art
In processor-based systems, read only memories (ROM) are configured to store information that has been written during the manufacturing process, but which cannot be written to during the normal operating process of the system. Random access memories (RAM) store information that can be directly and randomly read or written. The information stored in ROM is non-volatile (i.e., the information is retained when power is turned off), while that stored in RAM is volatile (i.e., information is lost when power is turned off). Boot routines and the PC BIOS routines are typically stored in ROM because information is retained when power is turned off.
However, information cannot be written to ROM and data that is stored in ROM typically cannot be altered, and when alteration is possible, it is difficult. As a result, an application program such as application software and/or firmware that is executed during power up or before RAM has been initialized and made accessible, has limited applications. This is because it cannot store information in ROM. For example, such application software cannot write e.g., store variables, build lists, or implement deeply nested procedures which utilize high level languages.
Accordingly, there is a need in the technology for an apparatus and method for overcoming the aforementioned problems. In particular, there is a need for an apparatus and method for enabling applications to write to a storage location prior to availability and accessibility of RAM in a processor system.
BRIEF SUMMARY OF THE INVENTION
An apparatus and method for accessing a writeable storage in a processor-based system. The apparatus comprises at least one writeable storage element and memory for storing instruction sequences by which the processor-based system is processed, that has at least one writeable storage location. A processor is coupled to the at least one writeable storage element and executes the stored instruction sequences. The stored instruction sequences include process steps to cause the processor to: (a) detect an access to the at least one writeable storage location; (b) transfer the access to the at least one writeable storage location to an access to the at least one writeable storage element; (c) process an instruction sequence corresponding to the access to the at least one writeable storage element.
REFERENCES:
patent: Re. 35480 (1997-03-01), DeLisle et al.
patent: 4926322 (1990-05-01), Stimac et al.
patent: 5255379 (1993-10-01), Melo
patent: 5274834 (1993-12-01), Kardach et al.
patent: 5276888 (1994-01-01), Kardach et al.
patent: 5280599 (1994-01-01), Arai
patent: 5283889 (1994-02-01), DeLisle et al.
patent: 5313585 (1994-05-01), Jeffries et al.
patent: 5530960 (1996-06-01), Parks et al.
patent: 5544344 (1996-08-01), Frame
patent: 5638532 (1997-06-01), Frame et al.
patent: 5758124 (1998-05-01), Ogata et al.
Anderson Matthew D.
Kim Matthew
Phoenix Technologies Ltd.
LandOfFree
Method and apparatus for RAM emulation using a processor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for RAM emulation using a processor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for RAM emulation using a processor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2443944