Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-09-19
2004-11-16
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S144000
Reexamination Certificate
active
06819150
ABSTRACT:
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
FIELD OF THE INVENTION
This invention relates to methods and apparatus for minimizing power consumption in electronic devices. In particular, this invention is directed to methods and apparatus for minimizing the amount of time the electronic device spends in a high power consumption mode.
BRIEF DESCRIPTION OF THE PRIOR ART
The prior art has attempted to minimize power consumption in electronic devices by having a sleep power mode wherein the power is turned off. While this type of operation conserves power, it presents the problem that the system requires wake-up time, in essence, time for transition out of this sleep mode and enter into an operation mode to be fully operational and to operate at full speed. Accordingly, there is either a delay in the operation that is required, or if there is no delay, there is a possibility that data may be lost during the wake up period. Neither of these possibilities is desirable and often neither is acceptable.
SUMMARY OF THE INVENTION
In accordance with the present invention, the above-noted problem of the prior art is resolved. The present invention provides a synchronization between an asynchronous mode clocking generator and a synchronous mode clocking generator. The circuits of the present invention switches between a high frequency clock and a lower frequency clock, in order to increase power saving.
As explained earlier, in a sleep mode, it is necessary to conserve the amount of energy as much as possible, therefore, it is desired to turn off most clocking operations and run only a smaller, critical, part of a circuit at a very low clocking speed because the lower the frequency, the less the power consumption. As such, it is needed to isolate the clocking generator device with the lowest clocking frequency during a sleep cycle.
As has been explained, the most convenient way of running at a low clocking speed is by using a “real time” clock generator, because the “real time” clock generator enables a convenient time range to synchronize the other clocking speeds as it has multiple time periods within the normal 32 kHz clock generator isolated.
The transition from either low power or “sleep” mode to a fully operation status is called “wake up” mode. Generally, in a system, when in “sleep” mode, it is necessary to use the clock source that is running very slow to run a part of the circuit that is needed to wake up the circuit.
Further, the “fast” clock and the “real time” 32 kHz clock are asynchronous to each other, also, the system clock and the 32 kHz clock are also asynchronous. Further, there remains a need to synchronize the fast clock, 32 kHz clock and the system clock.
When switching between the system clock and the 32 kHz clock, the 32 kHz clock is much slower than the system clock; therefore, during switching operations, a glitch may occur. Because the system clock is very important, if there is a glitch, the clocking signal may not function properly and a reliability issue may arise. Further, the glitch may cause the circuit itself not to function. Hence, any switching operation between the system clock and the 32 kHz clock must be done in a way to prevent the above problem.
Briefly, the circuit of the present invention waits for a clocking edge to switch from the system clock to the 32 kHz clock. Usually, at the rising edge of the 32 kHz clock, a switch from the system will be performed. Further, it is important that a switch does not occur in the middle of a clocking cycle as this can result in delays or glitches.
REFERENCES:
patent: 6269043 (2001-07-01), Batcher
patent: 6292038 (2001-09-01), Stachura et al.
patent: 6429698 (2002-08-01), Young
patent: 6453425 (2002-09-01), Hede et al.
patent: 6472909 (2002-10-01), Young
Kim Simon
Santosa Handiono
Wang Sheng Hung
Nu Ton My-Trang
Rogitz John L.
Sony Corporation
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