Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements
Reexamination Certificate
2002-07-15
2004-11-16
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Display driving control circuitry
Controlling the condition of display elements
Reexamination Certificate
active
06819337
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of graphics hardware and, more particularly, to a system for generating a digital video stream using a series of video routers.
2. Description of the Related Art
Within a digital system, it is often difficult to distribute a central clock signal to multiple locations with sufficiently low skew so as to establish a synchronous clock domain. This is especially true as clock frequencies increase and skew become a larger proportion of the total clock cycle time. Thus, there exists a need for a system capable of creating in effect a larger clock domain by allowing data communication across a cluster of smaller domains.
SUMMARY
In one set of embodiments, a method for initializing a linear series of video routers in a video processing system (e.g. a graphics accelerator) may be configured as follows. A host software routine, executing on a host computer coupled to the video processing system, may:
programmatically select one of a plurality of link interface buffers in each video router of the linear series to form a first video path. The host software may programmatically select one of a plurality of pixel clock signals to drive output from the link interface buffers of the first video path;
initialize read and write pointers of the selected link interface buffer in each video router of the first video path;
sequentially remove a reset condition from the link interface buffers of the first video path starting from the first video router of the linear series.
The sequential reset removal operation is started after the selected pixel clock signal has stabilized. This condition ensures that one video data word is read from and written to each link interface buffer of the first video path in each cycle of the selected pixel clock from the moment the reset condition is removed. Thus, the address separation between the read pointer and the write pointer of each link interface buffer remains relatively constant (and relatively close to the program selected pre-reset separation).
REFERENCES:
patent: 6147695 (2000-11-01), Bowen et al.
Alan Dare Perspectives on Image Quality in the Silicon Graphics® Infinite Reality Graphics System, Feb. 8, 2000, 5 pages.
Bella Matthew C.
Brightwell Mark K.
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Singh Dalip K.
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