Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Patent
1997-12-31
1999-10-05
Auve, Glenn A.
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
712215, 712226, G06F 1338
Patent
active
059616156
ABSTRACT:
A queue structure includes a plurality of entries, a plurality of ports coupled to the entries, a plurality of enable lines coupled to the entries and the ports, and control logic. Each enable line is adapted to enable a selected port to communicate with a selected entry. The control logic is adapted to enable at least two enable lines and allow at least one of the ports to communicate with at least two of the entries concurrently. A method for storing data in a queue is provided. The queue includes a plurality of entries, a plurality of ports coupled to the entries, and a plurality of enable lines coupled to the entries and the ports. Each enable line is adapted to enable a selected port to communicate with a selected entry. The method includes receiving a first instruction on one of the ports. A first enable line is enabled to allow the port to communicate with a first entry. The first instruction is stored in the first entry. A second enable line is enabled concurrent with enabling the first enable line to allow the port to communicate with a second entry. The first instruction is stored in the second entry.
REFERENCES:
patent: 5611063 (1997-03-01), Loper et al.
patent: 5737636 (1998-04-01), Caffo et al.
patent: 5751983 (1998-05-01), Abramson et al.
patent: 5881262 (1999-03-01), Abramson et al.
Morrison Michael J.
Zaidi Nazar A.
Zaveri Bharat
Auve Glenn A.
Intel Corporation
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