Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2006-07-11
2006-07-11
Elamin, A. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S400000, C713S401000, C713S500000, C713S501000, C713S600000, C713S601000
Reexamination Certificate
active
07076680
ABSTRACT:
One embodiment of the present invention provides a system that provides skew compensation for communications across a source-synchronous self-timed network. During each clock period, the system allows multiple synchronous transmitters to each transmit one data element and to assert one acknowledgement on a transmit clock line into the self-timed network. In doing so, the multiple synchronous transmitters do not wait for requests from the self-timed network before transmitting a subsequent data element. Similarly, during each clock period, the system allows multiple synchronous receivers to accept one data element from and to assert one request on a receive clock line coupled into the self-timed network. In doing so, the multiple synchronous receivers do not wait for acknowledgments from the self-timed network before receiving a subsequent data element. The self-timed network is configured to tolerate bounded skew between the multiple synchronous transmitters and multiple synchronous receivers.
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Elamin A.
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
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