Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-10-22
2001-06-05
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C331S057000, C713S401000
Reexamination Certificate
active
06243784
ABSTRACT:
TECHNICAL FIELD
The present invention relates to electrical circuitry, and more particularly to a technique for generating accurate delay of electrical signals.
BACKGROUND OF THE INVENTION
In asynchronous bus isolating/bridging applications, such as a SCSI isolator or bus extender, signals need to be precisely delayed by a predetermined amount in order to guarantee or even improve setup or hold times on the resultant output bus. Current techniques involve the use of a dynamically varying string of standard cells (such as inverters or buffers), of length determined by comparison to a reference delay or clock, to achieve a fixed delay. The delay elements are duplicated throughout the chip. This approach is large, very difficult to test and not very precise.
It is desirable to provide a precise delay circuit that is small. In addition, the delay elements should be tolerant of process, voltage, and temperature variations. The following techniques achieves all these goals.
SUMMARY OF THE INVENTION
The present invention is directed to a method and apparatus for generating precise delays of electrical signals. The approach is based on a phase-locked loop (PLL), and uses a reference clock, typically a crystal oscillator, as a timing reference. This removes the necessity of using a self calibration feature. The PLL locks to the reference clock, generating some integer multiple of the reference frequency. The PLL has a voltage-controlled oscillator (VCO) that is made up of a string of delay elements. These delay elements are precisely controlled by the closed loop dynamic of the PLL. Hence, the delay is precisely controlled by the timing reference. By using a PLL with a timing reference, we can achieve the goals of process, voltage, and temperature insensitivity. We then duplicate the delays (which make up the VCO) to particular locations on the chip where a controlled delay is needed. In the preferred embodiment, the delay cells are current controlled. In this case, a number of currents are distributed throughout the chip to the delay cells. Finally, programmability can be incorporated by using a number of delay cells and selecting the desired delay through a multiplexer.
To summarize, we provide a precise delay that is generated by a timing reference via a PLL. The delay is then duplicated across the chip in the form of a delay cell which is current controlled. The delay cells tend to be much smaller than existing solutions. The techniques described hereinbelow reduce gate count from those of prior techniques, which saves chip area, test time and overall chip cost.
It is thus an object of the present invention to provide a precise delay of an electrical signal.
It is another object of the present invention to provide a method for delaying an electrical signal when propagating from one electrical element/device to another.
It is yet another object of the present invention to provide a delay technique using a phase-locked loop.
It is still another object of the present invention to provide a high precision programmable delay element.
It is yet another object of the present invention to provide an improved bus isolator/bridge circuit.
It is yet another object of the present invention to provide an improved bus isolator/bridge circuit having controllable delay elements.
Those having normal skill in the art will recognize the foregoing and other objects, features, advantages and applications of the present invention from the following more detailed description of the preferred embodiments as illustrated in the accompanying drawing.
REFERENCES:
patent: 5175452 (1992-12-01), Lupi et al.
patent: 5221863 (1993-06-01), Motegi
patent: 5561692 (1996-10-01), Maitland et al.
patent: 5621360 (1997-04-01), Huang
patent: 5638030 (1997-06-01), Du
patent: 5900762 (1999-05-01), Ramakrishnan
patent: 6034570 (2000-03-01), Warwar
Anderson Michael B.
Jander Mark J.
Tabor Gregory A.
Auve Glenn A.
LSI Logic Corporation
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