Method and apparatus for providing precise circuit delays

Details Method and apparatus for providing precise circuit delays Method and apparatus for providing precise circuit delays

1996-06-28

2000-09-05

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710129, 375361, 375373, 327262, H03H 1126

Patent

active

061157694

ABSTRACT:
A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

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