Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-09-05
2000-11-07
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 30, 714726, 714727, 714729, 714733, 714734, G06F 900
Patent
active
061450979
ABSTRACT:
The present invention relates in general to a data processing system (10), and more particularly to a method and apparatus for providing operand feed forward support in a data processing system (10). In one embodiment, a scan chain (100) may be combined with a feed forward source Y (FFY) bit (64) to allow a user to update registers (50) and memory (18) during emulation and debug. In one embodiment, feed forward control circuitry (60) forces the content of the WBBR register (70) to be used as the Y source operand value for the first instruction to be executed following an update of scan chain (100). This allows debug module (14) to update processor registers (50) and/or memory (18) by initializing the WBBR register (70) with the desired value, asserting the FFY bit (64), and executing a processor (12) move instruction to the desired register in registers (50).
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Author unknown, Definitions for various computer terminology, www.OneLook.com, published Jun. 1997.
Motorola Inc. 1990, "M68300 Family CPU32 Central Processor Unit Reference Manual", Section 7 Development Support, pp. 7-1 through 7-31.
Motorola Inc. 1995, "DSP56300 24-Bit Digital Signal Processor Family Manual", Section 10 On-Chip Emulator (OnCE.TM.), pp. 10-1 through 10-29.
Motorola Inc. 1995, "DSP56300 24-Bit Digital Signal Processor Family Manual", Section 11 JTAG (IEEE 1149.1) Test Access Port, pp. 11-1 through 11-9.
Arends John
Moyer William C.
Beausoliel, Jr. Robert W.
Bonzo Bryce
Hill Susan C.
Motorola Inc.
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