Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1996-12-23
1999-11-23
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
G06F 1100
Patent
active
059918918
ABSTRACT:
A method and apparatus for providing loop coherency between a multiplicity of nodes. The disclosed technique and apparatus utilize a primary loop for nominal data communications and a normally unutilized secondary loop. A loop coherency circuit detects a loop incoherency condition which results in a interruption of the primary loop. The loop coherency circuit reroutes the flow of data to a secondary loop segment and back to a primary loop segment to provide a continuous coherent arbitrated loop.
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New Peripheral Interfaces: Fast & Full of Features; M. Wright; EDN Electrical Design News; vol. 40, No. 21, Oct. 12, 1995; pp. 69/70, 72, 74, 76, 78, 80, 81.
Hahn Dennis J.
Stover Jeremy D.
Beausoliel, Jr. Robert W.
Elisea Pierre E.
LSI Logic Corporation
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