Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2000-03-31
2003-09-30
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S005000, C711S202000, C711S220000
Reexamination Certificate
active
06629219
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memory addressing. More specifically, the present invention relates to a method and apparatus for providing highly programmable memory mapping and improved interleaving.
2. Background Information
Memory mapping is the process of translating a nominal memory address (issued e.g. by a processor) to an actual memory address appropriate for accessing a memory array. Such translation is necessary as data are often stored in an interleaving manner to decrease overall latency of systems and improve memory access times. Interleaving is a technique that involves dividing a memory array into two or more sections such that successive memory access requests can be directed to different sections of the memory. A system that performs 4-way interleaving, for example, will typically divide a corresponding memory into four sections. By directing the accesses to different sections of memory, overlapping memory requests may be made without interfering with each other thereby decreasing the need for the processor to insert wait states.
Unfortunately, however, conventional memory mapping systems typically require that all slots or rows within a memory array be populated and/or all memory devices within a memory array be of the same size in order to be interleaved. For example, assume that a given memory array consists of four rows of Synchronous Dynamic Random Access Memory (SDRAM) in which row
1
contains a 128 MB memory module, row
2
contains a 64 MB memory module, row
3
contains a 64 MB memory module and row
4
is empty. Conventional systems would not be capable of interleaving between the various rows of memory because rows
1
through
4
contain varying amounts of memory. Even if rows
1
through
3
each contained 64 MB of memory, however, some conventional systems would nonetheless still not be able to interleave unless row
4
contained the same amount of memory as rows
1
through
3
(64 MB).
SUMMARY OF THE INVENTION
According to one aspect of the invention, a multi-bit transaction address is received that specifies one or more memory locations of a memory array having at least one individually addressable memory row. The multi-bit transaction address is mapped to an intermediate memory address through a logical partitioning of the memory array into a plurality of individually addressable memory blocks such that each of the memory blocks are interleavingly accessible independent of how the memory array is populated. The memory array is then accessed using said mapped intermediate memory address.
REFERENCES:
patent: 5530837 (1996-06-01), Williams et al.
patent: 5848258 (1998-12-01), Fenwick et al.
patent: 6131146 (2000-10-01), Aono
patent: 6185654 (2001-02-01), Van Doren
patent: 0540198 (1993-05-01), None
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Moazzami Nasser
LandOfFree
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