Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1994-12-12
1996-08-20
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
36518902, 36523002, G11C 1300
Patent
active
055485537
ABSTRACT:
A semiconductor memory device according to the invention includes a main memory array comprising a plurality of memory sub-arrays. Each of the memory sub-arrays comprises a plurality of columns and at least one redundant column. Each column of the memory sub-array also includes multiplexing means, coupled to the input and output path of the respective column and an input and output path of a neighboring column. In addition, the redundant column is coupled to the input and output path of a neighboring column. In the event that one of the columns of the memory sub-array is defective, the multiplexing means of each of the columns between the defective column and the redundant column acts to couple the input and output paths of that column to the input and output paths of the neighboring column. With such an arrangement, the defective column is bypassed and a memory device capable of operating without defects is provided.
REFERENCES:
patent: 4598388 (1986-07-01), Anderson
patent: 4603404 (1986-07-01), Yamauchi et al.
Cooper Elizabeth M.
Leary Michael
Digital Equipment Corporation
Fears Terrell W.
Fisher Arthur W.
Maloney Denis G.
McGuinness Lindsay G.
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