Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1997-09-30
2002-04-30
Yoo, Don Hyun (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S114000, C711S130000, C711S118000
Reexamination Certificate
active
06381674
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to caching within a data storage subsystem and in particular to controller element(s) used as intelligent central cache apparatus within multiple redundant controller data storage subsystems.
2. Discussion of Related Art
Modern mass storage subsystems are continuing to provide increasing storage capacities to fulfill user demands from host computer system applications. Due to this critical reliance on large capacity mass storage, demands for enhanced reliability are also high. Various storage device configurations and geometries are commonly applied to meet the demands for higher storage capacity while maintaining or enhancing reliability of the mass storage subsystems.
A popular solution to these mass storage demands for increased capacity and reliability is the use of multiple smaller storage modules configured in geometries that permit redundancy of stored data to assure data integrity in case of various failures. In many such redundant subsystems, recovery from many common failures can be automated within the storage subsystem itself due to the use of data redundancy, error codes, and so-called “hot spares” (extra storage modules which may be activated to replace a failed, previously active storage module). These subsystems are typically referred to as redundant arrays of inexpensive (or independent) disks (or more commonly referred to by the acronym RAID). The 1987 publication by David A. Patterson, et al., from University of California at Berkeley entitled
A Case for Redundant Arrays of Inexpensive Disks
(
RAID
), reviews the fundamental concepts of RAID technology.
RAID storage subsystems typically utilize a control module that shields the user or host system from the details of managing the redundant array. The controller makes the subsystem appear to the host computer as a single, highly reliable, high capacity disk drive. In fact, the RAID controller may distribute the host computer system supplied data across a plurality of the small independent drives with redundancy and error checking information so as to improve subsystem reliability.
In some RAID configurations a portion of data is distributed across a plurality of data disk drives and associated redundancy information is added on an additional drive (often referred to as a parity drive when XOR parity is used for the redundancy information). In such configurations, the related data so distributed across plurality of drives is often referred to as a stripe. In most RAID architectures, the “write” operation involves both a write of the data to the data disk and also an adjustment of parity information. The parity information adjustment may involve the reading of other data in the same stripe and writing of the newly computed parity for the blocks of the stripe. This imposes a large “write penalty” upon RAID systems (RAID levels 3-6), often making them slower than traditional disk systems in the typical write I/O operation.
Known RAID subsystems provide cache memory structures to further improve the performance of the RAID subsystem write operations. The cache memory is associated with the control module such that the storage blocks on the disk array are mapped to blocks in the cache. This mapping is also transparent to the host system. The host system simply requests blocks of data to be read or written and the RAID controller manipulates the disk array and cache memory as required.
It is taught in co-pending U.S. patent application Ser. No. 08/772,614 to provide redundant control modules sharing access to common storage modules to improve subsystem performance while reducing the failure rate of the subsystem due to control electronics failures. In such redundant architectures as taught by co-pending U.S. patent application Ser. No. 08/772,614, a plurality of control modules are configured such that they control the same physical array of disk drives. As taught by prior designs, a cache memory module is associated with each of the redundant control modules. Each controller will use its cache during control of the data storage volume which it accesses.
In this configuration, the controllers gain the advantage of being able to simultaneously handle multiple read and write requests directed to the same volume of data storage. However, since the control modules may access the same data, the control modules must communicate with one another to assure that the cache modules are synchronized. Other communications among the cooperating controllers are used to coordinate concurrent access to the common resources. Semaphore locking and related multi-tasking techniques are often utilized for this purpose. The control modules therefore communicate among themselves to maintain synchronization of their respective, independent cache memories. Since many cache operations require the controllers to generate these synchronization signals and messages or semaphore locking and releasing messages, the amount of traffic (also referred to as coordination traffic or cache coordination traffic) generated can be substantial. This coordination traffic imposes a continuing penalty upon the operation of the data storage subsystem by utilizing valuable bandwidth on the interconnection bus as well as processing overhead within the multiple control modules. If not for this overhead imposed by coordination traffic, the data storage subsystem would have more bandwidth and processing power available for I/O processing and would thus operate faster.
In such a configuration wherein each control module has its own independent cache memory (also referred to herein as decentralized cache), there is significant duplication of the circuits and memory that comprise the cache memory on each control module. This duplication increases the complexity (and therefore the cost of manufacture) of the individual control modules. A decentralized cache architecture subsystem is scaled up by addition of control modules, each with its own duplicated cache memory circuits. This added complexity (and associated costs) therefore makes simple scaling of performance problematic.
In view of the above it is clear that a need exists for an improved cache architecture for redundant control module data storage subsystems which improves data storage subsystem performance and scalability while reducing duplication and complexity of known designs.
SUMMARY OF THE INVENTION
The present invention solves the above and other problems, and thereby advances the useful arts, by providing an intelligent central cache shared among a plurality of storage controllers in a storage subsystem. An intelligent central cache is a cache cooperatively engaged with the control modules (storage controllers) to provide caching within the storage subsystem. Various functions are performed within the intelligent central cache including storage, generation, and maintenance of cache meta-data, stripe lock functions to enable coordinated sharing of the central cache features, and functions to coordinate cache flush operations among the plurality of attached control modules.
By contrast, a “dumb” (unintelligent) cache, though it may be a centralized resource, is one used merely as a memory bank, typically for myriad purposes within the data storage subsystem. The intelligent cache of the present invention shares with the attached controllers much of the control logic and processing for determining, for example, when, whether, and how to cache data and meta-data in the cache memory. Cache meta-data includes information regarding the type of data stored in the cache including indications that corresponding data is clean or dirty, current or old data, and redundancy (e.g., RAID parity) data or user related data. The intelligent central cache of the present invention generates, stores, and utilizes cache meta-data for making such determinations relating to the operation of the central cache independently of and/or cooperatively with the storage controllers of the subsystem. Furthermore, the intelligent central cache of the p
DeKoning Rodney A.
Weber Bret S.
LSI Logic Corporation
McLean Kimberly
Yoo Don Hyun
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