Method and apparatus for providing a readable and writable cache

Details Method and apparatus for providing a readable and writable cache Method and apparatus for providing a readable and writable cache

1996-05-17

1999-09-28

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

G06F 1200

Patent

active

059604565

ABSTRACT:
A Cache Memory Controller which operates in conjunction with a TAG Random Access Memory (TAG RAM) coupled to the lower order bits on a host address bus is provided. The Cache Memory Controller selects the data to be written to TAG RAM from two or more sources. One of these sources provides snoop address signals and another provides invalidating signals. During a read operation, the lower order bits of the address on the address bus address the TAG RAM while the n higher order bits are passed to a shifter and to a compare circuit. In response to the lower order bits of the address provided, the TAG RAM generates an n-bit TAG data output signal. If this data output compares exactly with the n higher order bits on the host address bus, the compare circuit will indicate a hit. If the compare circuit does not indicate a hit, the n higher order address bits are written into the TAG RAM. Data from main memory is then loaded into the cache memory. During a write operation, the lower order bits address the TAG RAM, with the n higher order being passed to the shifter as before. Upon the occurrence of a TAG write enable signal, the output of the shifter is written into the TAG RAM as data at the TAG RAM address corresponding to the address on the lower order address lines of the host bus. Data is then loaded from main memory into the cache memory.

REFERENCES:
patent: 4794523 (1988-12-01), Adan et al.
patent: 4939641 (1990-07-01), Schwartz et al.
patent: 5287481 (1994-02-01), Lin
patent: 5497470 (1996-03-01), Liencres
patent: 5535358 (1996-07-01), Kimura et al.

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